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“One Student One Chip”Initiative�Learn to Build RISC-V Chips from Scratch with MOOC

OSOC Team

2025.07

Telegram Group

Website: ysyx.org/en

Email: ysyx@bosc.ac.cn

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1. Background

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The One Student One Chip (OSOC) Initiative

  • Launched in 2019 by UCAS(University of Chinese Academy of Sciences)
  • Learning-by-doing: Teach students to build real chips
  • Non-profit: Free learning for everyone, free tape-out for students
  • Open: Everyone is welcomed
  • Learn-on-demand

One

Student

Chip

One

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  • Allowing a student to graduate with a processor chip designed by herself/himself
  • Five senior undergraduates of UCAS participated
  • Completed the design of a 64-bit RISC-V processor in four months
  • The chip was taped out with 110nm and ran Linux and a self-built UCAS-core OS successfully

The 1st OSOC (Aug to Dec, 2019)

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NutShell: A Linux-Compatible RISC-V Processor Designed by Undergraduates�(1st OSOC processor chip)

  • 110nm process
  • 10mm2
  • 200mw@350MHz Typical
  • TQFP100 package
  • Single-issue, 9-stage, in-order
  • RV64IMAC,support M/S/U
  • BPU with PHT,512-entry BTB,16-entry RAS
  • Sv39, hardware TLB refill
  • 32K L1I & L1D
  • Read consistency for L1I & L1D
  • 128K L2 cache,next line prefetch
  • Develop with Chisel
  • SDRAM, SPI flash, UART
  • Support Linux 4.18.0 kernel
  • Support Busybox
  • Can boot Debian 11 on Emulator & FPGA

A 64-bit RISC-V Processor

Tape-out w/ 110nm process

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NutShell: Open-sourcing

  • Open-sourced on GitHub
    • NutShell: #Fork > 245

6

  • OpenEuler, an OS developed by Huawei, is booted successfully on NutShell

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Feedback from students

The working principles in the architecture course are straight-forward, often just a few short lines. However, implementing them in code turned out to be far more challenging than I had imagined.

Professor Hu Weiwu once said that as CS students, we should learn how to build computers, not just how to use them. I did not fully appreciate this statement before; in fact, I once questioned whether it was reasonable for the cs curriculum at UCAS to include so much hardware content. However, it was only after getting involved in real projects that I realized the knowledge and skills learned in university are truly valuable.

From user to creator

Compared to myself four months ago, the most significant change is this shift in mindset. When facing bugs, I no longer stubbornly focus on one point. Instead, I tell myself that bugs are written by people, and as long as I have patience and dig deep enough, I will definitely find the problem.

More confidence, more patience

The biggest difference compared to previous experiments is that there are no detailed step-by-step instructions from predecessors. Instead, I have to find my own methods, implement them independently, and then validate the results—even if it means starting over from scratch.

Self-exploring

Empower students!

It was only after getting involved in this project that I realized course assignments are like a ready-made orchard where you simply pick the fruit, whereas a project is more like being handed a barren piece of land and a few saplings. You have to do everything yourself—from clearing the ground to planting and fertilizing—without knowing whether the effort will bear fruit. For some reason, it feels like the fruit grown from scratch tastes sweeter.

Accomplishment

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Report Accepted by RISC-V Global Forum 2020

NutShell: A Linux-Compatible RISC-V Processor Designed by Undergraduates

The only report given by undergraduates

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2. Current Teaching and Organization Model

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Explore Large-Scale (from 2021-)

1st

2nd

3rd

4th

5th

6th

2024

2025

Acc. Enrolls

5

16

776

2529

4410

7788

10181

12491

Update on:2025/06/29

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OSOC Course Design

Application

Runtime

(Simple) OS

ISA(RISC-V)

Micro-architecture

Circuit

Synthesis

Physical design

Physical verification

GDSII

CS

EE

Everyone is welcomed. NO limitation on

  • university
  • major
  • grade
  • basis

Software

Chip

EDA

XiangShan

OoO

Cache

Extension

Branch Prediction

IP

Prefetch

Coherency

U-boot

UEFI

OpenSBI

Linux

GCC

LLVM

QEMU

Route

Place

Clock tree

Education equality

Full-stack training

Enter community or company

Floorplan

Standard cell

Timing analysis

Equivalence

Technology mapping

SW & HW co-design

Logical design & Physical design co-ordination

Based on open-sourced, practice-oriented, open learning

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Learning Roadmap

  1. A
  2. C
  3. B
  4. A

Fill a form

[~10 mins]

sh $ cat hello.c

#include <stdio.h>

int main() {

printf(“Hello YSYX!\n”);

return 0;

}

Preliminary

[1~2 months]

Interview

[~15 mins]

Basic

[~2 months]

Advanced

[~3 months]

Debug Exam

[~1 hour]

PLL

VGA

UART

SPI

SoC Integration

[~1 week]

Physical design

[~2 months]

Tapeout

[2~4 months]

Packaging

[~2 weeks]

PCB Testing

[~1 week]

Run demos

[~1 week]

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OSOC Organization Method

  • Teaching Assistant Team: Train high-quality offline TAs (advanced level), combined with online TAs (basic or advanced level)
  • Let students guide other students(peer tutoring): advanced level TAs participate in SIG projects while also mentoring 'beginner' and 'intermediate' students

Students from the uiversities

Train talent by levels:

Experts: 10%

Advanced: 30%

Basic: 60%

Recruit a large number of students (2000–4000), with a strict assessment process for registration (admitting 25%), while ensuring the proportions:

TA : Stu = 1:30

Chip Companies

Open-source Communities

Universities Research Institutions

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Learning Materials are opened

Teaching with slides, codes and demos

Account in Bilibili.com

  • Course Website
  • Handouts(260,000 words)
  • Slides(>800 pages, 85,000 words)
  • Videos(> 40 hours)

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Handouts in English Version are available

BREAKING: New handouts will be released this month(ysyx.org/en),

featuring a more beginner-friendly design.

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Learning Stage Division(New handouts)

  • Small, simple system -> Large, complex system
  • Small program -> Real program

Stage F, E

1+2…+10

3 inst.

9 inst.

Single-Cycle

Device(sim)

RT-Thread

RV32E(45 inst.)

Single-Cycle

Device(RTL)

Single-Cycle

Stage D

Super Mario

Stage C

Super Mario

RT-Thread

RV32E(45 inst.)

Pipeline+cache

Bus+SoC

Stage B

Super Mario

Device(RTL)

Self-design OS/Linux

Pipeline+cache

RV32GC(~100 inst.)

+Privilege

+MMU

Bus+SoC

Stage A

PAL (game)/Debian

Device(RTL)

Self-design OS/Linux

RV32GC(~100 inst.)

+Privilege

+MMU

Bus+SoC

Stage S

PAL (game)/Debian

Device(RTL)

OoO

+ arch. opt.

Entrance

Interview

Minimum CertificationLevel

Minimum

Tape-out Level

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Learning Notes of a student

Date

Task

Time dedicated

Issues encountered

How to solve

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Students' learning notes and meeting attendance

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No Deadline for Learning

  • The time spent by students to finish learning varies (from weeks to years)
    • Different universities, different majors, different grades, different basics
    • Some of them learn more quickly than others
    • Some of them start earlier than others
    • Some of them are busier than others with their own courses

  • Students without any basics may spend > 500 hours
    • 500h: the time to take compulsory courses and finish all assignments
  • Students can always learn with her/his own timing schedule
    • Once she/he finishes, she/he can apply for interview/exam

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Online Debug Exam, instead of paper exam

  • When students apply for tape-out, TA will inject some bugs randomly in students' project
    • Including hardware, software, building and simulation system bugs

  • Required to debug within 1 hour in an online meeting
    • share screen throughout the entire process

  • To evaluate whether
    • student knows enough details in the whole project
    • student can analyze problem from the respect of sw-hw co-operation
    • student knows when to use the right tools during debugging
    • student can solve new problems by herself/himself

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Chip & Board

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Demo by students

  • A computer science student who began studying OSOC as a junior

  • Load Linux from flash and boot successfully, showing the CAS logo

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Delivering PCB to students

PCB designed by OSOC

Before delivering

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Brought up Chips, Ran OS & Applications

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Enroll Anytime, Open Year-Round

Telegram

Group

Website

ysyx.org/en

Scan the QR code or visit ysyx.org/en and click "Signup"

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3. Collaboration

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OSOC Roadshow Event

  • Our journey is ongoing, we warmly invite you to reach out and extend an invitation to OSOC to visit your location!

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Professor in Kazakhstan introduces OSOC in his class

  • Professor Nursultan Kabylkas, Nazarbayev University
    • Register an elective course in NU: Microprocessor Design and Verification 101(CS335)
    • Train the first batch of RISC-V processor chip design talents for Kazakhstan

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Kazakhstan Got its First Self-Designed Processor Chip from OSOC

  • In March 2025, student Olzhas in Kazakhstan got his own designed RISC-V chip and tested successfully
  • The chip is totally designed through OSOC and taped out by OSOC
  • The first self-designed processor chip, demonstrating a big milestone in Kazakhstan

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OSOC Base in Kazakstan Nazarbayev University

  • Professor Nursultan Kabylkas runs a lab, and most of the students there have joined the OSOC program
  • Now it becomes the base and the workshop for OSOC students at NU
  • Forming an active OSOC student community

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Professor in Japan adopts the OSOC program

  • Professor Nobuaki Kobayashi, Nihon University
    • Train students' RISC-V design skills and explore RISC-V-related research topics
    • Willing to organize students to translate the OSOC handouts into Japanese, to attract more Japanese students to study

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OSOC University Collaboration Pathway

Initial Stage

Plan A: Regularly provide learning reports

Applicable scenario: A small number of students begin their study

Plan C: Regularly provide reports + teaching exchange + assign TAs

Applicable scenario: A certain number of students are studying, and they form study groups

Advantages: Assign TAs to monitor student progress within the group and provide guidance and support

Plan B: Regularly provide reports + teaching exchange

Applicable scenario: Intention to initiate 'teaching collaboration' Advantages: OSOC provides targeted solutions for teaching collaboration

Plan D: Achieve OSOC credit certification

Applicable scenario: University officially recognize OSOC learning contents and award credits on it

Advantages: Combines students' extracurricular practice with academic credits, effectively motivating students to participate in

Strengthened Stage

Plan E: Set OSOC club/workshop

Advantages: Offcially make study study group and OSOC could provide some financial support

In-Depth Stage

Plan H: Offer OSOC Practical Courses

Advantages: Comprehensively cultivate students' knowledge across the entire front-end and back-end chain, as well as their hands-on practical skills

Plan I: Offer OSOC Bootcamp

Applicable scenario:University provides venue and resource support, while OSOC provides teaching organization

Advantages: Concentrated offline teaching and learning for students, with high learning efficiency, short duration

Plan J: Conduct research and teaching project collaboration

Applicable scenario: University and OSOC share common project collaboration goals

Advantages: Both parties contribute resources to tackle technical challenges and carry out research and development, with project validation and iteration experience used for curriculum reform

The plans are gradually deepened and can also be carried out at the same time.

Plan F: Integrate OSOC tools in courses

Applicable scenario: University adjusts courses to integrate relevant contents

Plan G: Integrate OSOC experiments in courses

Advantages: Enhance practical aspects of the class, develop students' hands-on skills

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Future Plan

  • Invite or attract more domestic and overseas students to participate
  • Improve and add more language versions of handouts
    • including but not limited to: Portuguese, Japanese, German, Russian, etc.
  • Establish deeper cooperation with some universities(domestic and overseas)
    • form large-scale study groups and workshops
    • introduce OSOC experiments in courses or as part of graduation projects
  • Connect more companies and institutions
    • provide greater and better employment opportunities for advanced-level students
  • Set overseas bases
    • provide venue for local students to gather and study offline

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Telegram

Group Chat

website

ysyx.org/en

Thank you!

For collaboration and communication, please contact via email: suxiaoke@ict.ac.cn

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FAQ

  • Q: Where can I register?

A: On the official website(ysyx.org/en), follow the signup process.

  • Q: Where can I find the study materials?

A: On the official website(ysyx.org/docs/en/)

  • Q: I am in a lower grade/attending an ordinary university/studying another major/have no prior knowledge, can I participate?

A: Yes, you can.

  • Q: I have already graduated, can I participate?

A: You could study as you want, but free tape-out will be only provided for students.

  • Q: When is the registration deadline?

A: It's open all the time, you can learn anytime.

  • Q: Are there any fees for registration and learning?

A: This is a free project — no fees will be charged.

  • Q: How is registration screened?

A: There is no screening, the project team encourages everyone to learn.

  • Q: How long does it usually take to study?

A: It varies from person to person, you can try for two weeks first.

  • Q: When do I need to finish the learning?

A: There is no deadline, finish the learning and apply for defense.

More FAQs