Basics of

Low Power VLSI Design

​

​

​

​

​

By,

Sharada Guptha M N

Assistant Professor

Department of ECE

SSIT, Tumakuru

Power: The rate at which energy is delivered or exchanged.

Analogy of power and energy is water and its flow rate.

​

• In VLSI chips electrical energy is converted into heat energy during its operations.

​

• The rate at which energy is taken from the source and converted to heat is power dissipation.
• This heat energy has to be dissipated from the chip to avoid increase in chip temperature which in turn may cause temporary or permanent circuit failure.

​

• Interest in low power chips and systems are driven by by both technical and business needs.

​

• Industry demand for low power consumer electronic products are quite rapidly increasing.

​

• Due to the increase in device density, speed and complexity there is demand for newer generations of semiconductor processing technologies.

​

​

​

Low power VLSI design is broadly classified into

1. Analysis
2. Optimization.

​

• Analysis problems are concerned with accurate estimation of power dissipation at different phases of design.
• The purpose is to increase the confidence – power consumption specifications are not violated.
• Analysis techniques differ from their accuracy and efficiency
• Accuracy depends on the availability of design information.
• Analysis techniques also form foundation for optimization.

​

• Optimization is a process of generating best design with given optimization goal without violating design specifications.
• Two types - manual optimization

- automatic design optimization

Major criteria to be considered to are impact to circuit delay which affects throughput and chip area which directly translates manufacturing costs.

Other factors also to be considered are testability, reliability, quality, reusability, risk, design cycle time

​

The task of a design engineer is to carefully weigh each design choice within specification constraints and select best implementation.

​

​

Evolution in Power Dissipation:

Courtesy: Practical Low Power VLSI Design, by Gary Yeap

Figure : Evolution in Power Dissipation

Need to worry about Power�

Courtesy: Practical Low Power VLSI Design, by Gary Yeap

Figure : Heat dissipation in Microprocessor

Need of Low Power

• Growth of battery-powered systems
• Users need for:
• Mobility
• Portability
• Reliability
• Cost
• Environmental effects

IC Design Space:

Courtesy: Practical Low Power VLSI Design, by Gary Yeap

Figure : IC Design Space

Power Impacts on System Design:

• Energy consumed per task determines battery life
• Second order effect is that higher current draws decrease effective battery energy capacity
• Current draw causes IR drops in power supply voltage
• Requires more power/ground pins to reduce resistance R
• Requires thick&wide on-chip metal wires or dedicated metal layers
• Switching current (dI/dT) causes inductive power supply voltage bounce ∝ LdI/dT
• Requires more pins/shorter pins to reduce inductance L
• Requires on-chip/on-package decoupling capacitance to help bypass pins during switching transients
• Power dissipated as heat, higher temps reduce speed and reliability
• Requires more expensive packaging and cooling systems

Facts ...

Moore´s Law - doubling transistors every 18 months

​

• Power is proportional to die area and frequency!
• In the same technology a new architecture has 2-3X in Die Area
• Changing technology implies 2X frequency

​

SCALING TECHNOLOGY ...

• Decreasing voltage
• Decreasing of die area
• Increasing C per unit area

( 0.7 scaling factor ) ( 0.5 scaling factor ) 43% !!!

This implies that the power density increase of 40% every generation !!!

Temperature is a function of power density and determinates the type of cooling system needed.

​

VARIABLES

​

• PEAK POWER ( worst case )

Today´s packages can sustain a power dissipation over 100W for up to 100msec >>> cheaper package if peaks are reduced

​

• ENERGY SPENT ( for a workload ) More correlated to battery life

Low Power Strategies:

• OS level :

PARTITIONING, POWER DOWN

• Software level :

REGULARITY, LOCALITY, CONCURRENCY

( Compiler technology for low power, instruction scheduling )

• Architecture level : PIPELINING, REDUNDANCY, DATA ENCODING

( ISA, architectural design, memory hierarchy, HW extensions, etc )

​

• Circuit/logic level : LOGIC STYLES, TRANSISTOR SIZING, ENERGY

RECOVERY

( Logic families, conditional clocking, adiabatic circuits, asynchronous design )

​

• Technology level : Threshold reduction, multi-threshold devices, etc

Power Consumption Estimation:

0

5

10

15

20

25

30

Arch

Layout

RTL Circuit

Levels of abstraction

Error estimation

power consumption

Courtesy: Practical Low Power VLSI Design, by Gary Yeap

Figure : Estimation of Power Consumption

Due to the relative high error rate in the architectural estimation ( no vision of the total area, circuit types, technology, block activity, etc )

IMPORTANT DESIGN DECISIONS MUST BE DONE AT ARCHITECTURAL LEVEL!

​

• Accurate power evaluation is done at late design phases
• Needs of good feedback between all the design phases

- Correlation between power estimation from low level to high level

TRY TO IMPROVE ACCURACY AT HIGH LEVEL

• Critical path based power consumption analysis ( CIRCUIT TYPES, TECHNOLOGY, ACTIVITY FACTOR )

​

• Thermal images based correlation analysis ( HOTTEST SPOTS LOCATION, COOLEST SPOTS

LOCATION, TEMPERATURE DIFFERENCES, TEMPERATURE

DISTRIBUTION )

Architectural Power Evaluation:

Architectural design partition

• Power consumption evaluation at block level

- Power density of blocks

( SPICE simulation, statistical input set, technology and circuit types definition )

• Activity of blocks and sub-blocks ( running benchmarks )
• Area ( feedback from VLSI design, circuits and technology defined )

​

• Try do define scaling factors that allow to remap the architectural power simulator when technology, area and circuit types change

​

• Try to reduce the error estimation at high level

Power Dissipation in CMOS:

Primary Components:

• Capacitor Charging (85-90% of active power)
• Energy is ½ CV² per transition
• Short-Circuit Current (10-15% of active power)
• When both p and n transistors turn on during signal transition
• Subthreshold Leakage (dominates when inactive)
• Transistors don’t turn off completely
• Diode Leakage (negligible)
• Parasitic source and drain diodes leak to substrate

C

L

Diode Leakage Current

Subthreshold Leakage Current

Short-Circuit Current

Capacitor

Charging Current

Courtesy: Practical Low Power VLSI Design, by Gary Yeap

Figure : Power Dissipation in CMOS

Sources of Power Dissipation:

• Dynamic power dissipations: whenever the logic level changes at different points in the circuit because of the change in the input signals the dynamic power dissipation occurs.
• Switching power dissipation.
• Short-circuit power dissipation.

​

• Static power dissipations: this is a type of dissipation, which does not have any effect of level change in the input and output.
• Leakage power.

Switching Power Dissipation:

• Caused by the charging and discharging of the node capacitance.

Courtesy: Practical Low Power VLSI Design, by Gary Yeap

Figure : Switching Power Dissipation

Switching Power Dissipation

• P_s/w= 0.5 * α * C_L* V_dd² * f_clk

– C_L physical capacitance, V_dd supply voltage, α switching activity, f_clk clock frequency.

• ^CL^{(i) = Σ}j ^CIN^{j + C}wire ^{+ C}par(i)

– C_IN the gate input capacitance, C_wire the parasitic interconnect and C_par diffusion capacitances of each gate[I].

• Depends on:
• Supply voltage
• Physical Capacitance
• Switching activity

Short circuit power dissipation:

• Caused by simultaneous conduction of n and p blocks.

Figure : Short circuit current

Courtesy: Practical Low Power VLSI Design, by Gary Yeap

Short circuit power dissipation :

where k = (k_n = k_p), the trans conductance of the transistor,

τ = (t_rise = t_fall), the input/output transition time, V_DD = supply voltage,

f = clock frequency, and V_T = (V_Tn = |V_Tp|), the threshold voltage of MOSFET.

​

• Depends on :
• The input ramp
• Load
• The transistor size of the gate
• Supply voltage
• Frequency
• Threshold voltage.

CMOS Leakage Current

• Leakage is a form of current that is generally not intended for normal operation of digital circuit.
• It exists as natural phenomenon of the semiconductor device operation.
• generally leakage current serves no useful purposes
• IN CMOS circuits , two major sources of leakage current are
• Reverse biased PN junction
• Sub threshold channel conduction current

Leakage power dissipation:

• Six short-channel leakage mechanisms are there:
• I₁ Reverse-bias p-n junction leakage
• I₂ Sub threshold leakage
• I₃ Oxide tunneling current
• I₄ Gate current due to hot-carrier injection
• I₅ GIDL (Gate Induced Drain Leakage)
• I₆ Channel punch through current

​

• I₁ and I₂ are the dominant leakage mechanisms

Leakage current in digital design:

• Sub threshold leakage and reverse biased junction leakage have very similar characteristic.
• in the order of pico ampere per device.
• very sensitive to process variation
• both increase dramatically with temperature and are relatively independent of operating voltage for given fabrication process.

​

• LEAKAGE CURRENT
• Difficult to measure, predict, or optimized
• large scale high performance digital chips – operate in high frequency regions.
• Small custom circuits especially analog circuits – leakage current analysis can be performed using SPICE simulation or simple rule of thumb calculation.

​

Static Current:

• Strictly speaking, digital CMOS circuits are not supposed to consume static current flow.
• All non leakage current in CMOS circuits should occur in transient when signals are switching .
• there are times when deviations from CMOS style circuit design are necessary.

Leakage power dissipation

Figure : Summary of leakage current mechanism

Courtesy: Practical Low Power VLSI Design, by Gary Yeap

PN Junction reverse bias current:

• The reverse biasing of p-n junction cause reverse bias current

– Caused by diffusion/drift of minority carrier near the edge of the depletion region.

where V_bias = the reverse bias voltage across the p-n junction, J_s = the reverse saturation current density and A = the junction area.

Sub Threshold Leakage Current:

• Caused when the gate voltage is below V_th.

Figure : Sub threshold current

Figure: Subthreshold leakage in a negative-

channel metal–oxide–semiconductor (NMOS) transistor.

Courtesy: Practical Low Power VLSI Design, by Gary Yeap

Reducing Power:

• Switching power ∝ activity*½ CV²*frequency
• (Ignoring short-circuit and leakage currents)
• Reduce activity
• Clock and function gating
• Reduce spurious logic glitches
• Reduce switched capacitance C
• Different logic styles (logic, pass transistor, dynamic)
• Careful transistor sizing
• Tighter layout
• Segmented structures
• Reduce supply voltage V
• Quadratic savings in energy per transition – BIG effect
• But circuit delay is reduced
• Reduce frequency
• Doesn’t save energy just reduces rate at which it is consumed
• Some saving in battery life from reduction in current draw

Reduce leakage and Static Current

Supply Voltage Scaling

• Switching and short circuit power are proportional to the square of the supply voltage.
• But the delay is proportional to the supply voltage. So, the decrease in supply voltage will results in slower system.

​

​

• Threshold voltage can be scaled down to get the same performance, but it may increase the concern about the leakage current and noise margin.

Switching Activity Reduction

• Two components:
• f: The average periodicity of data arrivals
• α: how many transitions each arrival will generate.
• There will be no net benefits by Reducing f.
• α can be reduced by algorithmic optimization, by architecture optimization, by proper choice of logic topology and by logic-level optimization.

Physical capacitance reduction

• Physical capacitance in a circuit consists of three components:
• The output node capacitance (C_L).
• The input capacitance (C_in) of the driven gates.
• The total interconnect capacitance (C_int).
• Smaller the size of a device, smaller is C_L.
• The gate area of each transistor determines C_in.
• C_int is determine by width and thickness of the metal/oxide layers with which the interconnect line is made of, and capacitances between layers around the interconnect lines.

Issues:

• Technology Scaling
• Capacitance per node reduces by 30%
• Electrical nodes increase by 2X
• Die size grows by 14% (Moore’s Law)
• Supply voltage reduces by 15%
• And frequency increases by 2X

This will increase the active power by 2.7X

Ultra Low Power System Design:

• Power minimization approaches:
• Run at minimum allowable voltage
• Minimize effective switching capacitance

Courtesy: Practical Low Power VLSI Design, by Gary Yeap

Thank You