CS-773 Paper Presentation��Hardware-Software Co-Design for

Brain-Computer Interfaces

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Prakhar Diwan �Misfits (#2)

180100083@iitb.ac.in

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Pictures adapted from Hardware-Software Co-Design for Brain-Computer Interfaces else mentioned

Outline

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1. Introduction
2. Background & BCI tasks
3. HALO
4. Evaluation
5. Conclusion & Discussion

Introduction

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What are BCIs?

• Brain-Computer Interfaces are devices which capture and influence the activity of neurons in the brain tissue.

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• They are classified into 2 categories:
• Invasive BCIs
• Non-invasive BCIs

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Non-invasive BCIs

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https://www.scifilogic.com/2021/04/invasive-vs-noninvasive-brain-computer.html

• Low fidelity of sensed signals

Invasive BCIs

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https://www.nih.gov/file/9396

• Higher fidelity of sensed signals

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• But stricter power constraints

Advancing research on Brain Functions

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https://www.emotiv.com/glossary/brain-research/

Prosthesis Control using Motor Cortex

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https://www.nih.gov/file/9396

Prosthesis Control using Motor Cortex

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https://www.nih.gov/file/9396

Prosthesis Control using Motor Cortex

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https://www.nih.gov/file/9396

Treatment of Neurological Diseases

FDA approves treatment via BCIs for:

• Epilepsy
• Parkinson’s disease
• Dystonia and more

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And this list is growing quickly

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https://www.epilepsy.com/learn/epilepsy-due-specific-causes/structural-causes-epilepsy/specific-structural-epilepsies

Treatment of Neurological Diseases

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https://www.ninds.nih.gov/About-NINDS/Impact/NINDS-Contributions-Approved-Therapies/Brain-stimulation-therapies-epilepsy

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BCI Research: A promising field

• Number of patients ~ 2 Lakh people
• Growth is recorded every year

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• Various firms have shown interest

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Relevance for CS 773

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*DRAM

Software

Architecture

Relevance for CS 773

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*DRAM

Software

Architecture

Relevance for CS 773

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*DRAM

Software

Architecture

Ultra low-power multi-accelerator SoC

Background & BCI Tasks

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BCI: High-Level View

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*DRAM

BCI: High-Level View

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*DRAM

~ 1 cm

~ 1 cm

BCI: High-Level View

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*DRAM

~ 1mm

BCI: High-Level View

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*DRAM

Microelectrode

BCI: High-Level View

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*DRAM

Record/stimulate 5-10 neurons

Microelectrode

BCI: High-Level View

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*DRAM

Microelectrode Array

BCI: High-Level View

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*DRAM

Record/stimulate hundreds of neurons

Microelectrode Array

BCI: High-Level View

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*DRAM

8-16 bits/sample at

20-50 KHz

BCI: High-Level View

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*DRAM

2.4Ghz

BCI: High-Level View

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*DRAM

Non-rechargeable

Rechargeable

BCI: High-Level View

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*DRAM

Non-rechargeable

Rechargeable

15 years

BCI: High-Level View

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*DRAM

Non-rechargeable

Rechargeable

15 years

Wireless, low power

Supported BCI Tasks

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HALO

Movement intent

Seizure prediction

Spike detection

Compression

Encryption

Supported BCI Tasks

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HALO

Seizure prediction

Analysis of neuronal firing patterns

FFTs, cross-correlation, and bandpass filters

Supported BCI Tasks

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HALO

Movement intent

Neuronal firing pattern indicates use of limb

Stimulate motor cortex

Supported BCI Tasks

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HALO

Spike detection

Detect spike in BCI itself

Lesser transmitted data

Supported BCI Tasks

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HALO

Compression

Lossless compression

LZ4, LZMA, DWT

Supported BCI Tasks

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HALO

Encryption

Future proof

AES 128 bits

BCI Requirements

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Power consumption < 15mW

Safety critical

BCI Requirements

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Power consumption < 15mW

Sensor data rate ~ 46 Mbps

Safety critical

High processing rate

BCI Requirements

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Power consumption < 15mW

Sensor data rate ~ 46 Mbps

Response time ~ 5-10 ms

Safety critical

High processing rate

Real-time

Low Flexibility for High Data BW: current

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*DRAM

Why is flexibility a concern for BCIs?

• Single-device for multiple solutions
• Personalized treatment helps more
• Reduction in cost
• Quicker FDA approval for modular design

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Tradeoff between Data BW and Flexibility

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*DRAM

Ideal Scenario

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*DRAM

HALO

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HW Architecture for LOw Power BCIs

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Flexibility

Performance

Power-Efficiency

HALO

Supporting common workloads

• Compression (LZ4, LZMA, DWT)
• Spike Detection (NEO, DWT)
• Movement Intent
• Seizure Prediction
• Encryption

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Hence total 8 distinct flows

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*DRAM

Observations on two ends

• General-purpose on low-power RISC-V µC:
• Exceeds power budget by a lot

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• App-specific by monolithic ASIC per BCI task:
• Poor scaling with area
• Exceeds power budget for some tasks

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• Need for finer-grained design than m-ASICs

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*DRAM

Key Observations

• Algorithms for BCI tasks can be split into different phases

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• Monolithic ASIC for a BCI task ran different phases at same frequency

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• Splitting of phases into processing elements (PEs)

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Two ideas to meet requirements

• Running each PE at minimum clock frequency tolerable for meeting performance needs

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• Sharing and reusing the common PEs among different BCI tasks

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HALO Architecture

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*DRAM

HALO: Compression (LZ4)

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*DRAM

HALO: Compression (LZMA)

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*DRAM

HALO: Compression (DWTMA)

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*DRAM

HALO: Spike Detection (DWT)

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*DRAM

HALO: Spike Detection (NEO)

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*DRAM

HALO: Movement Intent

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*DRAM

HALO: Seizure Prediction

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*DRAM

HALO: Encryption (AES)

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*DRAM

HW-SW Codesign Techniques Applied

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*DRAM

Kernel PE decomposition : Two ends

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COARSER GRANULARITY

Monolithic ASICs

Each Operator receives its PE

Kernel PE decomposition : Two ends

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COARSER GRANULARITY

Monolithic ASICs

Each Operator receives its PE

HALO

Example: Seizure Prediction Task

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function seizure_prediction (input):

fft_out = fft(input, NUM_FFT_POINTS)

bbf_out = bbf(input, LOW_FREQ, HIGH_FREQ)

xcorr_out = xcorr(input)

p1 = svm_prediction(fft_out)

p2 = svm_prediction(bbf_out)

p3 = svm_prediction(xcorr_out)

return ((p1+p2+p3)>0)

Example: Seizure Prediction Task

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function seizure_prediction (input):

fft_out = fft(input, NUM_FFT_POINTS)

bbf_out = bbf(input, LOW_FREQ, HIGH_FREQ)

xcorr_out = xcorr(input)

p1 = svm_prediction(fft_out)

p2 = svm_prediction(bbf_out)

p3 = svm_prediction(xcorr_out)

return ((p1+p2+p3)>0)

Sig-proc kernels -> natural boundaries

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function seizure_prediction (input):

fft_out = fft(input, NUM_FFT_POINTS)

bbf_out = bbf(input, LOW_FREQ, HIGH_FREQ)

xcorr_out = xcorr(input)

p1 = svm_prediction(fft_out)

p2 = svm_prediction(bbf_out)

p3 = svm_prediction(xcorr_out)

return ((p1+p2+p3)>0)

Sig-proc kernels -> natural boundaries

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function seizure_prediction (input):

fft_out = fft(input, NUM_FFT_POINTS)

bbf_out = bbf(input, LOW_FREQ, HIGH_FREQ)

xcorr_out = xcorr(input)

p1 = svm_prediction(fft_out)

p2 = svm_prediction(bbf_out)

p3 = svm_prediction(xcorr_out)

return ((p1+p2+p3)>0)

Benefits by 3x lower power consumption

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PE Locality Refactoring

• Some workloads don’t have natural boundaries, so they need to be refactored

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• Let’s understand this with LZMA task

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Example: LZMA Compression Task

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function LZMA_COMPRESSION(input):

output = list(lzma_header)

while data = input.get() do

best_match = find_best_match(data)

match_prob = count(match_table,best_match)

/count_total(match_table)

r1 = range_encode(match_prob)

output.push(r1)

increment_counter(match_table, best_match)

end while

return output

https://www.youtube.com/watch?v=Jqc418tQDkg https://www.youtube.com/watch?v=05RFEGWNxts

Example: LZMA Compression Task

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function LZMA_COMPRESSION(input):

output = list(lzma_header)

while data = input.get() do

best_match = find_best_match(data)

match_prob = count(match_table,best_match)

/count_total(match_table)

r1 = range_encode(match_prob)

output.push(r1)

increment_counter(match_table, best_match)

end while

return output

Data locality for kernel boundaries works

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function LZMA_COMPRESSION(input):

output = list(lzma_header)

while data = input.get() do

best_match = find_best_match(data)

match_prob = count(match_table,best_match)

/count_total(match_table)

r1 = range_encode(match_prob)

output.push(r1)

increment_counter(match_table, best_match)

end while

return output

PE Reuse Generalization

• Amongst BCI workloads, many common kernels such as FFT, DWT etc. are used

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• Seizure prediction ∩ Movement intent = fft

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PE Reuse Generalization

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function seizure_prediction (input):

fft_out = fft(input, NUM_POINTS=1024)

…………

return ……

function movement_intent (input):

fft_out = fft(input, NUM_POINTS=25)

…………

return ……

Summary

• Refactoring of Algorithms into different PEs
• Each PE operates at minimum frequency
• Asynchronous, circuit-switched network used for inter-PE communication
• Low-power embedded microcontroller
• Configuration of PEs into pipelines
• Support compute which is absent via PEs

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Evaluation

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“Lower the better”

HALO obeys the 15mW power budget unlike RISC-V and ASICs.

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Safe and Chronic use possible.

Impact of HW-SW

Co-Design

Techniques on

XCOR and LZMA

workloads

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“Lower the better”

For LZMA & DWTMA

Compression optimal

block size chosen

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“Higher the better”

LZMA gives better

compression ratio

but also consumes

more power

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Conclusion

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Conclusion

• Modular, flexible & configurable approach
• Power-efficient & adequate performance for safe and chronic usage of BCIs
• Easily scalable to incorporate future BCI tasks
• Inspires ultra-low power multi-acc SoC design

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HALO outperforming other devices

Discussion

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Discussion

• How will multiple-HALO implants fare?
• Can a network of them be realised?
• Will it maintain the power budget? ☹
• How to mitigate it? Any ideas
• Running parallel BCI tasks -> power budget ☹
• Effect of shared memory b/w PEs on power?
• Application to multi-acc SoC may require this
• Network complexity increases ☹

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BACKUP

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Spatial reprogramming Helps! Eg:XCOR

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Block-based processing leads to lethal burst mode computation

Spatial reprogramming Helps! Eg:XCOR

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Burst mode computation avoided by processing data as it arrives; by spatially reprogramming algorithm

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Detailed Task-wise power split into PEs

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PE Data-Locality based Refactoring