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實作專題介紹

鄭桂忠老師

Neuromorphic and Biomedical Engineering (NBME) LAB

NTHU - NBME

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仿生與生醫工程研究室

NTHU - NBME

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Contact Information

kttang@ee.nthu.edu.tw

+886-3-5162178

https://nbme.ee.nthu.edu.tw/

812R, Delta Building,

Dept. of Electrical Engineering, National Tsing Hua University,

Hsinchu 30013, Taiwan

鄭桂忠 教授 

Kea-Tiong (Samuel) Tang

Professor

Vice President, IEEE CASS

Past Chair, IEEE Taipei Section

Editor-in-Chief, TBioCAS

Department of Electrical Engineering

National Tsing Hua University

Research Interests

  • 仿神經人工智慧晶片 (系統A組+系統B組)

Neuromorphic AI chip

  • 電子鼻系統 (系統A組+系統B組)

Miniature Electronic Nose System

  • 生醫晶片與系統-醫用植入、腦機介面、神經輔具 (系統A組+系統B組)

Medical implant, brain-machine interface, neural prosthesis

  • 演算法、信號處理、類比電路、系統晶片 (系統A組+系統B組)

Algorithm, Signal processing, Analog circuit, System-on-chip

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專題題目

  • 數位電路專題：
    • 深度神經網路FPGA加速器(Deep Neural Network FPGA accelerator)
    • 突波神經網路FPGA加速器(Spiking Neural Network FPGA accelerator)

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  • 類比電路專題：
    • 生醫晶片關鍵電路
      • Bio-signal amplifier, low-power ADC, power regulator

NTHU - NBME

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深度/卷積神經網路FPGA加速器

  • 此專題將包括系統設計、神經網路實作(DNN, CNN)、FPGA系統實作等。

Input Image

FPGA System

Predict Result

DNN Deploy on FPGA

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神經群仿生神經網路處理器

NTHU - NBME

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  • 從仿生角度出發，此專題將包括突波神經網路設計(SNN)、FPGA系統實作等。

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A Low-Noise Neural Signal Amplifier with Adjustable Gain and Bandwidth for Capturing AP/LFP Signals Separately

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  • Low Noise, Low Power
  • Adjustable Gain
  • Adjustable Bandwidth (AP/LFP mode)

▲ Table1. Performance Table

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Implementation and Improvement of An Automatic Gain Control (AGC) Amplifier for Deep Brain Stimulation

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  • Low Noise, Low Power
  • Automatic adjustable Gain (prevent HVS)

▲ Table1. Performance Table

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A 6 bits 25MS/s 3b/cycle SAR ADC with Boundary Detection Code Overriding (BDCO)

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  • SAR + Flash A/D → Speed ↑, Efficiency ↑
  • Interpolation → Comparator Counts ↓
  • BDCO → Accuracy ↑, Power Consumption ↓

▲ Fig1. Block Diagram

▲ Fig2. Switching Scheme

▲ Fig3. Pre-sim Table

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A 10-bit 320kS/s SAR ADC design and application

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  • MSB-2 skip logic → Power Consumption ↓

▲ Table1. Performance Table

Item

Spec

This Work

Supply Voltage

1.2V

1.2V

Sampling Rate

320kS/s

320KS/s

SNDR (dB)

>56(dB)

>58.2(dB)

ENOB

>9bits

9.2bit

Power Consumption

< 5μW

4.82μW

▲ Fig.1 Block Diagram of SAR ADC

▲ Fig.2 Sample and hold circuit, S/H

▲ Fig.3 Comparator

▲ Fig.4 ADC work schematic waveform

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LDO PSR Enhancement with Current-mode FFRC and Loop Gain Stabilizer

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  • Operation point of EA and the loop gain of the LDO is stable

Loop Gain Stabilizer

Buffer

Current-mode FFRC

The output of the Error Amplifier (EA) is fixed at Ve

Buffer is added between MP and EA

  • High impedance of EA output and high capacitance of MP gate are split

Current-mode feedforward ripple cancellation (FFRC)

  • Power supply noise is cancelled, PSR is enhanced

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Digital LDO Transient Response Enhancement with VCO

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  • Low power supply can be achieved compared to analog LDO

Nearly all digital architecture

Voltage-controlled oscillator and adaptive clock are used

 

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電路設計專題相關競賽

  • IEEE Circuits and Systems Society (CASS) – �Student Design Competition

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NTHU - NBME

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5月

11月

競賽報名

初賽

1月

3月

複賽

@ IEEE ISCAS,

2026 上海

決賽

2025

2026

  • 教育部智慧晶片系統應用創新專題實作競賽
    • 重要時程(參考歷年):

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7月

初賽:摘要

4月

3月

初賽:報告

決賽

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專題說明

  • 希望學生具備之背景知識或建議選修課程
    • 電子學(實驗)、電路學(實驗)、邏輯設計(實驗)、程式設計、Verilog、FPGA、AIC、VLSI、IC Lab等
  • 進行方式: 每週與老師與研究生討論
  • 希望人數／組: 2-3人
  • 可接受組數: 各1-2組
  • 會學到的技術:系統考量與設計、雛型實作、電路設計、電路板或晶片製作、軟體撰寫
  • 面談資料: 成績單、組員、有興趣之題目
  • 有問題可直接寫信討論
    • kttang@ee.nthu.edu.tw