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Title: Introduction to VHDL, Latches and Flip-Flops

CO addressed: CO4

Course: Analog and Digital Electronics

Presented by: Prof. G Soujanya

Department: Artificial Intelligence and Machine Learning

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INTRODUCTION TO VHDL

The acronym VHDL stands for VHSIC-HDL (Very High Speed Integrated Circuit-Hardware Description Language).

• VHDL is a hardware description language that is used to describe the behavior and structure of digital systems. VHDL is a general-purpose hardware description language which can be used to describe and simulate the operation of a wide variety of digital systems.
• VHDL can describe a digital system at several different levels—behavioral, data flow, and structural. For example,
• A binary adder could be described at the behavioral level in terms of its function of adding two binary numbers, without giving any implementation details.
• The same adder could be described at the data flow level by giving the logic equations for the adder.
• Finally, the adder could be described at the structural level by specifying the interconnections of the gates which make up the adder.

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VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS

In VHDL, a signal assignment statement has the form:

The expression is evaluated when the statement is executed, and the signal on the left side is scheduled to change after delay.

• A VHDL signal is used to describe a signal in a physical system. The VHDL language also includes variables like variables in programming languages.
• In general, VHDL is not case sensitive, that is, capital and lower case letters are treated the same by the compiler and the simulator
• Signal names and other VHDL identifiers may contain letters, numbers, and the underscore character (_).

Figure has five signals: A, B, C, D, and E. The symbol “ <= ” is the signal assignment operator

Dataflow Description:

C <= A and B after 5 ns;

E <= C or D after 5 ns; Fig:4.1 Gate circuit

Initially A = 1, and B = C = D = E = 0; and if B changes to 1 at time 0, C will change to 1 at time = 5 ns. Then, E will change to 1 at time = 10 ns.

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• Behavioral Description: A behavioral description of the above circuit shown is

E <= D or (A and B);

Components may be declared and defined either in a library or within the architecture part of the VHDL code.

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Instantiation statements are used to specify how components are connected

The circuit shown is described by instantiating the AND gate and the OR gate as follows:

Gate1: AND2 port map (A, B, D);

Gate2: OR2 port map (C, D, E);

The port map for Gate1 connects A and B to the AND-gate inputs, and it connects D to the AND- gate output. Since an instantiation statement is concurrent, whenever A or B changes, these changes go to the Gate1 inputs, and then the component computes a new value of D.

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Similarly, the second statement passes changes in C or D to the Gate 2 inputs, and then the component computes a new value of E.

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The following Figure shows an inverter with the output connected back to the input.

• If the output is ‘0’, then this ‘0’feeds back to the input and the inverter output changes to ‘1’after the inverter delay, assumed to be 10 ns.
• Then, the ‘1’feeds back to the input, and the output changes to ‘0’after the inverter delay. The signal CLK will continue to oscillate between ‘0’and ‘1’, as shown in the waveform.

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Fig 4.2 Inverter with feedback

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The three concurrent statements execute simultaneously whenever A changes, just as the three gates start processing the signal change at the same time.

• However, if the gates have different delays, the gate outputs can change at different times.
• If the gates have delays of 2 ns, 1 ns, and 3 ns, respectively, and A changes at time 5 ns, then the gate outputs D, E, and F can change at times 7 ns, 6 ns, and 8 ns, respectively.
• However, if no delays were specified, then D, E, and F would all be updated at time 5 + ∆.

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Fig 4.3 Three gates with common input and different delays

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• In these examples, every signal is of type bit, which means it can have a value of ‘0’or ‘1’.
• In digital design, we often need to perform the same operation on a group of signals. A one-dimensional array of bit signals is referred to as a bit-vector.
• If a 4-bit vector named B has an index range 0 through 3, then the four elements of the bit-vector are designated B(0), B(1), B(2), and B(3). The statement B <= “0110”, assigns ‘0’to B(0), ‘1’to B(1), ‘1’to B(2), and ‘0’to B(3).
• The following Figure shows an array of four AND gates. The inputs are represented by bit-vectors A and B, and the outputs by bit-vector C.

Fig:4.4 Array of AND gates

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Inertial delay model: Signal assignment statements containing “after delay” create what is called an inertial delay model. Consider a device with an inertial delay of D time units. If an input change to the device will cause its output to change, then the output changes D time units later.

Example: consider the signal assignment C <= A and B after 10 ns;

Assume A and B are initially 1, and A changes to 0 at 15 ns, to 1 at 30 ns, and to 0 at 35 ns. Then C changes to 1 at 10 ns and to 0 at 25 ns, but C does not change in response to the A changes at 30 ns and 35 ns; because these two changes occurred less than 10 ns apart.

• Ideal (Transport) delay: VHDL can also model devices with an ideal (transport) delay.
• Output changes caused by input changes to a device exhibiting an ideal (transport) delay of D time units are delayed by D time units, and the output changes occur even if they occur within D time units. The VHDL signal assignment statement that models ideal (transport) delay is

Signal_name<= transport expression after delay

Example: consider the signal assignment C <= transport A and B after 10 ns;

Assume A and B are initially 1 and A changes to 0 at 15 ns, to 1 at 30 ns, and to 0 at 35 ns. Then C changes to 1 at 10 ns, to 0 at 25 ns, to 1 at 40 ns, and to 0 at 45 ns. Note that the last two changes are separated by just 5 ns.

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VHDL MODELS FOR MULTIPLEXERS

• The following Figure shows a 2-to-1 multiplexer (MUX) with two data inputs and one control input.

The MUX output is 𝐹 = 𝐴′ 𝐼0 + 𝐴𝐼1. The corresponding VHDL statement is F <= (not A and I0) or (A and I1);

• The MUX by a conditional signal assignment statement, F <= I0 when A = ‘0’ else I1;This statement executes whenever A, I0, or I1 changes.
• The MUX output is I0 when A = ‘0’, and else it is I1. In the conditional statement, I0, I1, and F can either be bits or bit-vectors.

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Fig 4.5: 2-to-1 multiplexer

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The following Figure shows how two cascaded MUXes can be represented by a conditional signal assignment statement. The output MUX selects A when E = „1‟; or else it selects the output of the first MUX, which is B when D = „1‟, or else it is C.

Fig 4.6: Cascaded 2-to-1 multiplexers

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The following Figure shows a 4-to-1 MUX with four data inputs and two control inputs, A and B. The control inputs select which one of the data inputs is transmitted to the output. The logic equation for the 4-to-1 MUX is 𝐹 = 𝐴′ 𝐵′𝐼0 + 𝐴′ 𝐵𝐼1 + 𝐴𝐵′𝐼2 + 𝐴𝐵𝐼3.

One way to model the MUX is with the VHDL statement

F <= (not A and not B and I0) or (not A and B and I1) or

(A and not B and I2) or (A and B and I3);

Another way to model the 4-to-1 MUX is to use a conditional assignment statement (given in Figure below):

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Fig 4.7: 4-to-1 multiplexer

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• The expression A&B means A concatenated with B, that is, the two bits A and B are merged together to form a 2-bit vector. This bit vector is tested, and the appropriate MUX input is selected. For example, if A = „1‟ and B = „0‟, A&B = “10” and I2 is selected.
• Instead of concatenating A and B, we could use a more complex condition also (as given in above Figure).

A third way to model the MUX is to use a selected signal assignment statement; we first set Sel equal to A&B. The value of Sel then selects the MUX input that is assigned to F.

The general form of a selected signal assignment statement is

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VHDL MODULES:

• To write a complete VHDL module, we must declare all of the input and output signals using an entity declaration, and then specify the internal operation of the module using an architecture declaration. As an example, consider the following Figure.
• When we describe a system in VHDL, we must specify an entity and architecture at the top level.

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Fig 4.8: VHDL modules with Two Gates

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When we describe a system in VHDL, we must specify an entity and architecture at the top level.

• The entity declaration gives the name “two_gates” to the module. The port declaration specifies the inputs and outputs to the module. A, B, and D are input signals of type bit, and E is an output signal of type bit.
• The architecture is named “gates”. The signal C is declared within the architecture because it is an internal signal. The two concurrent statements that describe the gates are placed between the keywords begin and end.

entity entity-name is

[port(interface-signal-declaration);]

end [entity] [entity-name];

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The items enclosed in square brackets are optional. The interface-signal-declaration normally has the following form:

list-of-interface-signals: mode type [: _ initial-value]

{; list-of-interface-signals: mode type [: _ initial-value]};

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The curly brackets indicate zero or more repetitions of the enclosed clause.

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Fig 4.9: VHDL program structure

Input signals are of mode in, output signals are of mode out, and bi-directional signals are of mode inout.�For example

port(A,B: in integer:= 2, C,D: out bit)

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architecture architecture-name of entity-name is

[declarations] begin architecture body

end [architecture] [architecture-name];

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Example: To write the entity and architecture for a full adder module.

The entity specifies the inputs and outputs of the adder module, as shown in the following Figure.

The port declaration specifies that X, Y and Cin are input signals of type bit, and that Cout and Sum are output signals of type bit.

Fig 4.10: Entity declaration for a full adder module

In the declarations section, we can declare signals and components that are used within the architecture. The architecture body contains statements that describe the operation of the module.

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The Full Adder module defined above can be used as a component in a system which consists of four full adders connected to form a 4-bit binary adder (see the following Figure).

First declare the 4-bit adder as an entity (see the following Figure). Since, the inputs and the sum output are four bits wide, declare them as bit_vectors which are dimensioned 3 down to 0.

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Fig 4.11: 4-bit binary adder

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• specify the Full Adder as a component within the architecture of Adder4

In the body of the architecture, create several instances of the Full Adder component. Each copy of Full Adder has a name (such as FA0) and a port map.

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• The signal names following the port map correspond one-to-one with the signals in the component port. Thus, A(0), B(0), and Ci correspond to the inputs X, Y, and Cin, respectively. C(1) and S(0) correspond to the Cout and Sum outputs.
• Note that the order of the signals in the port map must be the same as the order of the signals in the port of the component declaration.

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LATCHES:

Sequential switching circuits have the property that the output depends not only on the present input but also on the past sequence of inputs. In effect, these circuits must be able to “remember” something about the history of the inputs in order to produce the present output.

LATCHES & FLIP-FLOPS:

SET RESET LATCH:

A simple latch can be constructed by introducing feedback into a NOR-gate circuit,

if the inputs are S = R = 0, the circuit can assume a stable state with Q= 0 and P = 1.

1. S = 0 & R = 0: A stable condition of the circuit because P = 1 feeds into the second gate forcing the output to be Q = 0, and Q = 0 feeds into the first gate allowing its output to be 1.
2. S = 1 & R = 0: An unstable condition or state of the circuit because both the inputs and output of the second gate are 0; therefore Q will change to 1, leading to the stable state.

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Fig 4.12 Latch using NOR gate

Fig 4.13: SR latch

a) S = 0 & R = 0: The circuit will not change state because Q = 1 feeds back into the first gate, causing P to remain 0.

Note that the inputs are again S = 0 & R = 0, but the outputs are different than those with which we started. Thus, the circuit has two different stable states for a given set of inputs.

b) S= 0 & R = 1: Q will become 0 and P will then change back to 1.

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An input S = 1 sets the output to Q = 1, and an input R = 1 resets the output to Q = 0.

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The circuit is commonly referred to as a set-reset (S-R) latch (restriction that R and S cannot be 1 simultaneously).

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The stable states of the outputs P and Q are always complements, that is, P = Q’.

To emphasize the symmetry between the operation of the two gates, the circuit is often drawn in cross-coupled form, as shown in the following Figure (a).

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Fig 4.14: Different representations of SR latch

If S = R = 1, the latch will not operate properly, as shown in above Figure (c). Note that, when S and R are both l, P and Q are both 0. Therefore, P is not equal to Q’, and this violates a basic rule of latch operation.

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Fig 4.15: Timing diagram for S-R latch

Q(t) represent the present state and Q(t + ɛ) represent the next state,

considering Q(t) as an input and Q(t + ɛ) as the output. Then for the S-R latch;

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The equation for output P is:

These equations are mapped in the next-state and output tables as given

The stable states of the latch are circled. Note that for all stable states, P = Q except when S = R = 1. Making S = R = 1, a don’t-care combination allows simplifying the next-state equation.

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Table 4.1: S-R latch next state and output

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An equation that expresses the next state of a latch in terms of its present state and inputs will be referred to as a next-state equation, or characteristic equation.

An alternative form of the S-R latch uses NAND gates, as shown in the following Figure.

Fig 4.16: S-R latch

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Applications of S-R Latch:

S-R latch is often used as a component in more complex latches and flip-flops and in asynchronous systems. Another useful application of the S-R latch is for debouncing switches.

Debouncing switches

When a mechanical switch is opened or closed, the switch contacts tend to vibrate or bounce open and closed several times before settling down to their final position. This produces a noisy transition, and this noise can interfere with the proper operation of a logic circuit.

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Fig 4. 17: Switch debouncing with an S-R Latch

The input connected to a logic 1 (+ V). The pull-down resistors connected to contacts a and b assure that when the switch is between a and b the latch inputs S and R will always be at a logic 0, and the latch output will not change state.

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• Gated latch have an additional input called the gate or enable input. When the gate input is inactive, which may be the high or low value, the state of the latch cannot change.
• When the gate input is active, the latch is controlled by the other inputs and operates as indicated in the preceding section.
• A NAND gate version of gated S-R latch is show in Fig

Fig 4.18: NAND Gate Gated S-R Latch

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Table 4.2: Next state and output of Gated S-R latch

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Fig 4.19: Race condition in the gated S-R Latch

If the equation for Q+ is plotted on a Karnaugh map fig 4.20 it is evident that Q+ has a static 1- hazards.

For inputs G=1, S= 1, R=1, Q=1 and G=0, S= 1, R=1, Q=1.

Consequently, when G changes from 1 to 0 between these two input combinations, it is possible for Q to change from 1 to 0 and because of the feedback, to cause Q to remain at Q=0.

Fig 4.20: Karnaugh map for Q+

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GATED D LATCH:

A gated D latch (given in Figure below) has two inputs—a data input (D) and a gate input (G). The D latch can be constructed from an S-R latch by connecting S to D and R to D’. When G = 0, S = R = 0, so Q does not change. When G = 1 and D = 1, S = 1 and R = 0, so Q is set to 1. When G = 1 and D = 0, S = 0 and R = 1, so Q is reset to 0.

R = 1, so Q is reset to 0.

when G = 1, the Q output follows the D input,

when G = 0, the Q output holds the last value of D (no state change).

This type of latch is also referred to as a transparent latch

because when G = 1, the Q output is the same as the D input.

From the truth table, the characteristic equation for the latch is

𝑄+ = 𝐺′ 𝑄 + 𝐺𝐷.

Fig 4.21: Gated D latch

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Fig 4.22: Symbol and truth table for Gated Latch

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EDGE-TRIGGERED D FLIP-FLOP

A D flip-flop has two inputs, D (data) and Ck (clock). The small arrowhead on the flipflop symbol identifies the clock input. Unlike the D latch, the flip-flop output changes only in response to the clock, not to a change in D.

• If the output can change in response to a 0 to 1 transition on the clock input, we say that the flip- flop is triggered on the rising edge (or positive edge) of the clock.
• If the output can change in response to a 1 to 0 transition on the clock input, we say that the flip- flop is triggered on the falling edge (or negative edge) of the clock.
• An inversion bubble on the clock input indicates a falling-edge trigger (Figure (b)), and no bubble indicates a rising-edge trigger (Figure (a)).

Fig: 4.23: D Flip-Flops

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A rising-edge-triggered D flip-flop can be constructed from two gated D latches and an inverter, as shown in Figure the following Figure (a). The timing diagram is shown in Figure

Fig 4.24: D Flip-Flop (Rising edge Trigger)

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When CLK = 0, G1 = 1, and the first latch is transparent so that the P output follows the D input. Because G2 = 0, the second latch holds the current value of Q.

When CLK changes to 1, G1 changes to 0, and the current value of D is stored in the first latch. Because G2 = 1, the value of P flows through the second latch to the Q output.

Fig 4.25: Setup and hold times for an edge Triggered D flipflop

The amount of time that the D input must be stable before the active edge is called the setup time (tsu), and the amount of time that the D input must hold the same value after the active edge is the hold time (th). The times at which D is allowed to change during the clock cycle are shaded in the timing diagram of the following Figure.

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Consider the circuit of following Figure 4.26 (a). Suppose the inverter has a propagation delay of 2 ns, and suppose the flip-flop has a propagation delay of 5 ns and a setup time of 3 ns. (The hold time does not affect this calculation). Suppose, as in following Figure 4.26(b), that the clock period is 9 ns, i.e., 9 ns is the time between successive active edges (rising edges for this figure).

• Then, 5 ns after a clock edge, the flip-flop output will change, and 2 ns after that, the output of the inverter will change. Therefore, the input to the flip-flop will change 7 ns after the rising edge, which is 2 ns before the next rising edge. But the setup time of the flip-flop requires that the input be stable 3 ns before the rising edge; therefore, the flip-flop may not take on the correct value.
• Suppose instead that the clock period were 15 ns, as in following Figure 4.26(c). Again, the input to the flip- flop will change 7 ns after the rising edge. However, because the clock is slower, this is 8 ns before the next rising edge. Therefore, the flip-flop will work properly. Note in Figure 4.26 (c) that there is 5 ns of extra time between the time the D input is correct and the time when it must be correct for the setup time to be satisfied. Therefore, we can use a shorter clock period, and have less extra time, or no extra time. Figure 4.26(d) shows that 10 ns is the minimum clock period which will work for this circuit.

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Fig 4.27: Determination of minimum clock period

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S-R FLIP-FLOP:

An S-R flip-flop (following Figure) is similar to an S-R latch in that S = 1 sets the Q output to 1, and R = 1 resets the Q output to 0. The essential difference is that the flip-flop has a clock input, and the Q output can change only after an active clock edge.

Fig 4.28: S-R Flip Flop

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• The truth table and characteristic equation for the flip-flop are the same as for the latch, but the interpretation of Q⁺ is different.
• For the latch, Q⁺ is the value of Q after the propagation delay through the latch, while for the flip-flop, Q⁺ is the value that Q assumes after the active clock edge.
• The following Figure 4.28 (a) shows an S-R flip-flop constructed from two S-R latches and gates. This flip- flop changes state after the rising edge of the clock. The circuit is often referred to as a master- slave flip- flop.
• When CLK = 0, the S and R inputs set the outputs of the master latch to the appropriate value while the slave latch holds the previous value of Q.
• When the clock changes from 0 to 1, the value of P is held in the master latch and this value is transferred to the slave latch. The master latch holds the value of P while CLK = 1, and, hence, Q does not change.

When the clock changes from 1 to 0, the Q value is latched in the slave, and the master can process new inputs.

Figure 4.29 (b) shows the timing diagram. Initially, S = 1 and Q changes to 1 at t1. Then R = 1 and Q changes to 0 at t3.

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Fig 4.29 S-R flipflop implementation and timing

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• For a rising-edge-triggered flip-flop, the value of the inputs is sensed at the rising edge of the clock, and the inputs can change while the clock is low.
• For the master-slave flip-flop, if the inputs change while the clock is low, the flip-flop output may be incorrect. For example, (in above Figure (b)), at t4, S = 1 and R= 0, so P changes to 1.
• Then S changes to 0 at t5, but P does not change, so at t5, Q changes to 1 after the rising edge of CLK. However, at t5, S = R = 0, so the state of Q should not change. We can solve this problem if we only allow the S and R inputs to change while the clock is high.

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J-K FLIP-FLOP:

The J-K flip-flop (shown in the following Figure) is an extended version of the S-R flip-flop. The J- K flip-flop has three inputs—J, K, and the clock (CLK). The J input corresponds to S, and K corresponds to R.

If J = 1 and K = 0, the flip-flop output is set to Q = 1 after the active clock edge;

If K = 1 and J = 0, the flip-flop output is reset to Q = 0 after the active edge.

Unlike the S-R flip-flop, a 1 input may be applied simultaneously to J and K, in which case the flip- flop changes state after the active clock edge.

When J = K = 1, the active edge will cause Q to change from 0 to 1, or from 1 to 0.

The next-state table and characteristic equation for the J-K flip- flop are given in Figure (b).

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(c) J-K Flip Flop timing

Fig 4.30: J-K Flip Flop (Q changes on the Rising edge)

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Figure (c) shows the timing for a J-K flip-flop. This flip-flop changes state a short time (tp) after the rising edge of the clock pulse, provided that J and K have appropriate values.

If J = 1 and K = 0 when Clock = 0, Q will be set to 1 following the rising edge. If K = 1 and J = 0 when Clock = 0, Q will be set to 0 after the rising edge.

Similarly, if J = K = 1, Q will change state after the rising edge. Referring to Figure 11-29(c), because Q= 0, J = l, and K = 0 before the first rising clock edge, Q changes to 1 at t1.

Because Q = 1, J = 0, and K = 1 before the second rising clock edge, Q changes to 0 at t2. Because Q = 0, J = 1, and K = 1 before the third rising clock edge, Q changes to 1 at t3.

One way to realize the J-K flip-flop is with two S-R latches connected in a master-slave arrangement, as shown in the following Figure.

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Fig 4.31: Master slave J k flipflop (Q changes on Rising Edge)

This is the same circuit as for the S-R master-slave flip-flop; except S and R have been replaced with J and K, and the Q and Q’ outputs are feeding back into the input gates. Because S = JQ’Clk’ and R = K’QClk’, only one of S and R inputs to the first latch can be 1 at any given time. If Q = 0 and J = 1, then S = 1 and R = 0, regardless of the value of K. If Q = 1 and K = 1, then S = 0 and R = 1, regardless of the value of J.

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The T flip-flop, also called the toggle flip-flop, is frequently used in building counters. Most CPLDs and FPGAs can be programmed to implement T flip-flops.

The T flip-flop has a T input and a clock input. When T = 1 the flip- flop changes state after the active edge of the clock. When T = 0, no state change occurs.

The next-state table and characteristic equation for the T flip-flop are given in Figure (b). The characteristic equation states that the next state of the flip-flop (Q⁺) will be 1 iff the present state (Q) is 1 and T = 0 or the present state is 0 and T = 1.

T FLIP-FLOP:

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Fig 4.31: Timing diagram for T Flip Flop (Falling Edge trigger)

One way to implement a T flip-flop is to connect the J and K inputs of a J-K flip-flop together, as shown in the following Figure (a). Substituting T for J and K in the J-K characteristic equation gives;

𝑄+ = 𝐽𝑄′ + 𝐾′ 𝑄 = 𝑇𝑄′ + 𝑇′𝑄

which is the characteristic equation for the T flip-flop.

​

fig 4.32 (a) Conversion of J-K to T

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Another way to realize a T flip-flop is with a D flip-flop and an exclusive-OR gate [Figure (b)]. The D input is Q ⊕ T, so Q⁺ = Q ⊕ TQ’ + T’Q, which is the characteristic equation for the T flip-flop.

Fig 4.32: b) Conversion D to T Flip Flops

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SR flipflop:

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JK flipflop:

​

​

​

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D flipflop:

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T flipflop:

​

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T flipflop from SR flipflop:

​

S = TQn’ & R = TQn

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Therefore, the circuit diagram for conversion of S-R flip-flop into T flip-flop is:

​

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T flipflop from JK flipflop:

 Step-1: Construct the characteristic table of T flip-flop and excitation table of the J-K flipflop.

​

Step-2: Using the K map, find the boolean

expression for J and K in terms of T

J = T K = T

Step-3: Construct the circuit diagram for the

conversion of the J-K flip-flop into a T flip-flop.

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T flipflop from D flipflop:

Step 3: Write the conversion table

The conversion table, which is a combination of truth table and excitation table, to implement a T flip-flop from D flip-flop is as follows

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Step 4: Find the Boolean expressions for the inputs of the given flip-flop

Therefore, write the Boolean expression for D from the conversion table using K-Map.

K-Map for D:

​

Expression for D = T^’Q_N + TQ_N^’