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AstroPix A-STEP�Electrical Systems

D. Durachka

R. Boggs

10/26/2023

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Introduction

  • Grounding Configuration
  • Board Definitions
    • Power Distribution Unit (PDU)
    • Detector Bias Board
    • FPGA Board
    • Chip Carrier
  • Command and Telemetry
  • Interface Control Documentation

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Power Distribution Unit

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Power Distribution Unit

  • 6-Layer board
  • DC-DC Converters:
    • PDQ30-Q24-S5-D Manufactured by CUI
    • Successfully used these on the COM-PAIR balloon mission.
  • U1 will provide 5.3V to the Detector Bias and FPGA Boards
  • U2 will provide 5.0V to the Beagle Bone CPU
    • Harness descriptions and design are covered in the ICD
  • Power Returns and Grounding
    • Power Returns are kept separate from the Chassis GND
    • Outputs are AC Coupled to chassis via 0.1uF capacitor
    • 4-40 mounting holes are all connected to chassis (9 mounting holes)
    • Mounting holes for D-SUB Connectors are also connected to chassis

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Detector Bias Board

  • J1: Receives 5.3V from PDU
  • J2: Command and Telemetry with FPGA board
  • J3: 5.3V and Return for FPGA board
  • P1 – P6 provide biasing and returns for detectors on the chip carriers
  • 6-layer board

Ultra Volt

0.2US5-N0.1

(0V 🡪 -200V)

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Grounding Configuration and Zap Trap

  • Chassis and Secondary Return
    • D1 and D2 form zap trap
    • JP4 will not be populated
  • Detector Bias Power and Returns
    • P1, P3, P5: Bias
    • P2, P4, P6: Bias Return
  • 4-40 Mounting holes are connected to chassis

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Bias Board Command and Telemetry Points

  • Command & Telemetry Points
    • Detector Bias Set Point
    • Detector Bias Read
    • Detector Current Sense
      • All three detectors are read separately via LT5400BIMS8E-1#PBF resistor array
      • Each resistor is read by an INA284 current sense amplifier
      • AD590MF temp transducer is epoxied to the array via Stycast 2850/Cat9
    • Did not have enough I/O’s available to track the temp during flight, will monitor this during testing and compare to other values that are being tracked.

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  • DC-DC Converter is the 0.2US5-N0.1 manufactured by Ultra Volt

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  • Baseline Bias Value: -150V
    • Control voltage: 1.875V
    • Detector Bias Read is also 0 🡪 2.5V
  • Expected Current Draw from Detector is 200nA.
    • Resistor array houses values of 10K
    • INA284 provides a gain of 200

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Control Voltage

Output DC Level

0V

0V

2.5V

-200V

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FPGA Board Overview

  • The FPGA board shall provide these functions for the A-STEP system:
    • Power regulation for the three carrier board layers
    • 8 channels of system telemetry
    • A DAC for controlling the HV power supply
    • Level shifters to step down the 3.3v FPGA logic to 1.8v logic for the carrier boards
    • A 100 MHz sample clock for the carrier boards
    • SPI busses and other digital communication with each carrier board

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Board Dimensions

  • Board Dimensions:
    • 75.112 mm x 63.15 mm
  • Mounting Hole Size:
    • #4-40
  • 8 Layers

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Telemetry

  • 8 channels of telemetry provided by ADC128S102:
    • Three temperature monitors (one per carrier board)
    • Carrier board current monitor
    • HV supply monitor
    • Three HV supply current monitors

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Power Conditioning (Carrier Board/FPGA Power)

  • Regulating +5.3v sounding rocket power to +4.5v
  • LP38501 Current Limit: 3A
    • Estimated current draw: TBD

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Power Conditioning (Other)

  • Regulate +5.3v sounding rocket power to +3.3v and +1.8v
  • +3.3v powers ADC, DAC, and Level Shifter B-Sides
  • +1.8v powers Level Shifter A-Sides
  • LT3080 Current Limit: 1.1A
    • +3.3v Current Draw: TBD
    • +1.8v Current Draw: TBD

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HV Power Supply Control DAC

  • DAC121S101 supplies analog control voltage from FPGA for the HV supply.
  • Output range: 0v – 3.3v

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Sample Clock Schematic

  • Single FPGA pin generates 100 MHz clock
  • LVDS Driver (SN65LVDS1DBVR) converts single-ended signal to LVDS
  • LVDS Repeater (SN65LVDS104D) splits into 3 LVDS signals (one per carrer board)

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Sample Clock Layout

Layer 5 (GND)

Layer 6

Layer 7 (GND)

FR4

11.811 mil

11.811 mil

5 mil

5.263 mil

5 mil

LVDS Coupled Stripline Impedance Control Dimensions

(1 oz Copper)

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Level Shifters

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Power Connection to Beaglebone

  • Plan to power the Beaglebone via the battery connection
    • Not using barrel connection due to vibration concerns.
    • Documentation for Beaglebone confirms that we can use TP5 and TP8 to power the Beaglebone

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Communication with FPGA Board

  • The Beaglebone will serve as the SPI Master
    • Reset Synchronizer

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    • pll_locked: Provided by the MMMC resource, ensures reset is only released after clocks are stable
    • warm_resn: External signal, triggers reset without stopping clocks
    • cold_resn: Asserts reset in all clock domains, then stops MMMC resource to stop all clocks

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Beaglebone Communication with Sounding Rocket

  • Sounding rocket side:
    • RS-422 communication standard
  • Beaglebone Black side:
    • RS-485 Cape
      • RS-422 is a point-to-point com standard, RS-485 is capable of multi-drop
      • When not transmitting, RS-485 transmitter goes into tri-state mode
    • Wallops engineers are verifying their hardware can handle this

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Backup Slides

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PDU Backup

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PDU Input Network and Layout

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PDU Output Network and Layout

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Detector Bias Board Backup

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Input power and regulator

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Aliveness Testing

  • PDU and Detector Bias Boards require dummy loads to do aliveness testing
    • Procured leaded resistors, will breadboard them as loads for the PDU and Detector Bias Boards
  • FPGA aliveness testing
    • TBD