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�BASIC COMPUTER ORGANIZATION & DESIGN�

S.ROHINI

Assistant professor

Department of CS & IT

CPA college

Bodinayakanur

Cardamom Planters’ Association College

(Re-accredited with ‘B’ Grade by NAAC)

Pankajam Nagar, Bodinayakanur – 625513

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CONTENT

TIMING & CONTROL

The timing for all registers in the basic computer is controlled by a master clock generator.
The clock pulses are applied to all flip-flops and registers in the system, including the flip-flops and registers in the control unit.
The clock pulses do not change the state of a register unless the register is enabled by a control signal.
The control signals are generated in the control unit and provide control inputs for the multiplexers in the common bus, control inputs in processor registers, and micro operations for the accumulator.
There are two major types of control organization:

The differences between hardwired and micro programmed control are

Hardwired control	Micro programmed control
The control logic is implemented with gates, flip-flops, decoders, and other digital circuits.	The control information is stored in a control memory. The control memory is programmed to initiate the required sequence of micro operations.
The advantage that it can be optimized to produce a fast mode of operation.	Compared with the hardwired control operation is slow.
Requires changes in the wiring among the various components if the design has to be modified or changed.	Required changes or modifications can be done by updating the micro program in control memory.

TIMING & CONTROL UNIT BLOCK DIAGRAM

It consists of two decoders, a sequence counter, and a number of control logic gates.
An instruction read from memory is placed in the instruction register (IR). It is divided into three parts: The I bit, the operation code, and bits 0 through 11.
The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. The eight outputs of the decoder are designated by the symbols D0 through D7
Bit 15 of the instruction is transferred to a flip-flop designated by the symbol I.
Bits 0 through 11 are applied to the control logic gates.
The 4-bit sequence counter can count in binary from 0 through 15.
The outputs of the counter are decoded into 16 timing signals T0 through T15.

The sequence counter SC can be incremented or cleared synchronously.
The counter is incremented to provide the sequence of timing signals out of the 4 x 16 decoder.
As an example, consider the case where SC is incremented to provide timing signals T0, T1, T2, T3 and T4 in sequence. At time T4, SC is cleared to 0 if decoder output D3 is active.
This is expressed symbolically by the statement D3T4: SC <-0
The sequence counter SC responds to the positive transition of the clock. Initially, the CLR input of SC is active. The first positive transition of the clock clears SC to 0, which in turn activates the timing signal T0 out of the decoder. T0 is active during one clock cycle.
SC is incremented with every positive clock transition, unless its CLR input is active.
This produces the sequence of timing signals T0, T1, T2, T3, T4 and so on, as shown in the diagram.

Output D3 from the operation decoder becomes active at the end of timing signal T2.
When timing signal T4 becomes active, the output of the AND gate that implements the control function D3T4 becomes active.
This signal is applied to the CLR input of SC. On the next positive clock transition (the one marked T4 in the diagram) the counter is cleared to 0.
This causes the timing signal T0 to become active instead of T5 that would have been active if SC were
incremented instead of cleared.