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We would like to acknowledge Triton Quantitative Trading, the National Research Platform, and YC from Digikey for providing the resources for this project.

A Low Latency, High Frequency Trading System

Brendon Chang, Tristan Lee, Yahir Salas, Mustahsin Zarif, Philip Pincencia, Marc Boudames

Triton Quantitative Trading, University of California, San Diego

Acknowledgements

Modern High Frequency Trading (HFT) systems must process millions of messages per symbol in the stock market.

Goal:

Optimize the machines to react and trade on market data in microsecond intervals
Optimize the runtime of decoding ethernet packets, making a decision, and then sending it back to the NASDAQ stock exchange.

Bridge the Gap between finance and engineering
Develop a low latency pipeline:

Market Data

Synthetic Strategy

Outputs a decision based strategy.

Optimize our pipeline for academic research in the future

Motivation

Objectives

Run Synthesis on all our upstream modules independently
Resolve Timing Violations
Run full pipeline implementation on Nautilus

Future Work

Why Field Programmable Gate Arrays (FPGAs)

Reprogrammable, redistributable
Parallel Processing
Accelerates hardware

Latency Calculation:

Background

Results

Figure 1: Total Simulated Execution Time for the Ethernet decoder, MoldUDP64 decoder, and order book decision making tree

Pipeline / Methodology

Figure 2: Measuring the amount of correct packets measured in each stage. ITCH Parser Stage failed in our simulation, we are currently working on that

Figure 3: Throughput and Order Flow of the Pipeline Executed at 100gbps and Random Jitter Speeds

On average, we measured ~ 230 ns in our simulated pipeline, which is significantly smaller than our projected 1 microsecond intervals.

All modules passed the packet correctness test, except the Intelligent Tick-by-Tick High-Frequency (ITCH) Parser which is due to incorrect syntax errors when we simulated the pipeline.

There are no packet congestions at a steady state 100gbps flow.

Analysis