Digital Electronics
BRANCH-E&TC ENGINEERING
SEM – 3Rd
SUBJECT-DIGITAL ELECTRONICS
CHAPTER-01
TOPIC-basic of digital electronics
FACULTY-ER S MOHANTA.
CHAPTER 8 PREVIEW
OVERVIEW OF COUNTERS
CHARACTERISTICS OF COUNTERS
RIPPLE COUNTER
0 0 0 0
0 0 0 1
Binary Output
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
Pulse 1
Clock Input
All J-K flip-flops
in the
TOGGLE MODE
PS and CLR input
are
INACTIVE
Pulse 2
Pulse 3
Pulse 4
Pulse 5
Pulse 6
Pulse 7
Pulse 8
On the next clock pulse (8) all FFs
will toggle because each will receive
a H-to-L pulse- one after another.
Watch the count ripple thru the counter.
This 4-bit counter has 16 states and
will count from binary 0000 through 1111
and then reset back to 0000.
The counter has a modulus of 16.
RIPPLE COUNTER WITH WAVEFORMS
0 0 0 0
0 0 0 1
Binary Output
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
Pulse 1
Clock Input
Pulse 2
Pulse 3
Pulse 4
Pulse 5
Clock input
1s output
2s output
4s output
FFs triggered on
H-to-L pulse.
CLK toggles 1s FF.
1s FF toggles 2s FF.
2s FF toggles 4s FF.
DECADE COUNTER
Binary Output
0 1 1 1
1 0 0 0
Pulse 1
Clock Input
Pulse 2
Pulse 3
Pulse 4
Pulse 5
Pulse 6
Pulse 7
Pulse 8
To change mod-16 counter to decade counter:
Reset count to 0000 after 1001 (9) count.
When count hits 1010 reset to 0000.
See added 2-input NAND gate that clears all
JK FFs to 0 when count hits 1010.
1 0 0 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
Count is at 1001.
Next clock pulse will increment counter for a
short time to 1010 which will activate the NAND gate
and reset the counter to 0000.
Initial count at 0111
Short negative pulse
To clear input
of each FF
All J & K inputs = 1
All PR inputs = 1
DOWN COUNTER
Changes from Ripple Up Counter are
wiring from Q’ outputs (instead of Q outputs)
to the CLK input of the next FF.
Pulse 1
Pulse 2
1 1 1
1 1 0
Initial count
set at
binary 111
1 0 1
Pulse 3
Pulse 4
1 0 0
0 1 1
Pulse 5
0 1 0
SELF-STOPPING DOWN COUNTER
Pulse 1
Pulse 2
Pulse 3
Pulse 4
Pulse 5
1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
This is a 3-bit down counter.
The 1s FF is in TOGGLE mode when counting (J & K = 1).
The 1s FF switches to HOLD mode when the J and K inputs are forced LOW by the OR gate
when the count decrements to 000. The count stops at 000.
0 0 1
Pulse 6
0 0 0
Pulse 7
Pulse 8
Watch count on
Pulse 8.
The count remained
at binary 000.
COUNTER USED FOR FREQUENCY DIVISION
Clock Input
800 Hz
400 Hz
200 Hz
100 Hz
50 Hz
÷ 2
÷ 4
÷ 8
÷ 16
USING THE 7493 COUNTER IC
7493 Counter IC
wired as a 4-bit
binary counter
1600 Hz
? Hz
800 Hz
? Hz
100 Hz
? Hz
400 Hz
MAGNITUDE COMPARATOR
A magnitude comparator is a combinational logic device that compares the value of two binary numbers and responds with one of three outputs (A=B or A>B or A<B).
Input binary 0001
Input binary 1100
HIGH
HIGH
Input binary 1111
Input binary 0110
Input binary 0111
Input binary 0111
HIGH
74HC85
Magnitude
Comparator
A = B
A < B
A > B
A(0)
A(1)
A(2)
A(3)
B(0)
B(1)
B(2)
B(3)
TROUBLESHOOTING EQUIPMENT
SIMPLE TROUBLESHOOTING HINTS