FOSS SILICON

SERV, Edalize and OpenMPW

THE RIGHT ENGINEERS

AT THE RIGHT TIME

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Todays topic

• Introducing some of the ecosystem for free and open source digital circuit design
• Told through the story of my experience with taping out SERV, a free and open source RISC-V processor
• Tapeout done through the Google-financed OpenMPW program, using the required Openlane toolchain

1

2023-10-12

Who I am

• Education background in electrical engineering at Chalmers, master program in embedded electronic system design
• Previous experience with ASIC work at Ericsson, embedded software and FPGA experience with various companies...
• Currently employed by 2550 Engineering, a part of the Qamcom Group
• Part of the hardware team at Zeropoint Technologies

2

2023-10-12

A few useful terms...

• EDA - Electronic Design Automation
• ASIC - Application Specific Integrated Ciruit, in our context as opposed to FPGA
• FPGA – Field Programmable Gate Array
• Tapeout – the act of sending an integrated circuit design to production

3

2023-10-12

Qamcom Group in open hardware

• Strategic member of RISC-V International
• While not Qamcom-driven projects, the tools Edalize and Fusesoc as well as the processor SERV are maintained and originally written by Qamcom employee Olof Kindgren

4

2023-10-12

How are digital ASICs made?

• Write the design in a hardware description language (SystemVerilog, VHDL...)
• Verify the code with a simulator and possibly formal proofs
• Give constraints such as clock frequency
• Optimize and express as gates with a LOGIC SYNTHESIS tool
• Place components, route wires with a PLACE AND ROUTE tool

5

2023-10-12

How are digital ASICs made?

• The tools mentioned do not do the lowest level of layout - a library of STANDARD CELLS, most importantly physical layout of individual logic gates, is needed
• Also physical models, design rules...
• Together called a Process Design Kit (PDK)

6

2023-10-12

How are digital ASICs made?

For a completely FOSS tapeout, major tools needed include

• FOSS simulator
• FOSS logic synthesis
• FOSS place and route
• FOSS process design kit
• FOSS layout tool

All of this exists!

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2023-10-12

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2023-10-12

What is RISC-V?

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• Open instruction set architecture
• Importantly an open standard, not a particular FOSS processor design
• Both several proprietary and several FOSS implementations exist

9

2023-10-12

What is RISC-V?

• An ISA specifies the hardware-software interface, implementations can differ
• Basic integer instruction sets of 32-bit instructions working with 32, 64 or 128 bit registers and addresses
• Various optional extensions, such as floating point, compressed instructions, less privileged modes...
• Originally developed at UC Berkeley, now maintained by RISC-V International headquartered in Switzerland

10

2023-10-12

What is OpenMPW?

• OpenMultiProjectWafer – program funded by Google to produce open source ASICs for free together with Efabless and the Skywater foundry
• Uses Skywater 130nm procses
• Requires the Openlane flow – a collection of FOSS tools to take your design from code to physical layout

11

2023-10-12

What is OpenMPW?

OpenMPW requires using a "harness" called Caravel, including a pad frame and a VexRiscv processor domain that can you connect to your design with GPIOs and a Wishbone bus

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2023-10-12

What is OpenMPW?

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2023-10-12

Openlane

The Openlane flow scripts together several separate open source projects, including

• Yosys for logic synthesis
• Openroad for for placement, global routing
• Tritonroute for detailed routing
• Magic for layout

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2023-10-12

15

2023-10-12

My project in OpenMPW

• Me and my colleague Olof Kindgren�got funding from NLnet to create�an Openlane backend for the�tool Edalize
• As part of this, tape out the�RISC-V processor SERV�as proof of concept

16

2023-10-12

What is Edalize?

• FOSS EDA tool abstraction library
• Generate configuration for specific�tool from common files and run�the tool
• Backends for several simulators,�synthesis tools and more
• https://github.com/olofk/edalize

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17

2023-10-12

What is Fusesoc?

• Edalize is used as part of Fusesoc,�a package manager for FPGA�and ASIC projects
• Have your project automatically�retrieve dependencies through�Fusesoc and build it with Edalize
• https://github.com/olofk/fusesoc

18

2023-10-12

SERV

• Very small FOSS RISC-V processor – roughly 2100 gates in minimal configuration
• Implements just the basic 32-bit integer instruction set in our case 
• Design existed earlier than this project - just an adaption
• How does it get so small? Bit-serial!

19

2023-10-12

SERV

• A typical processor with 32 bit registers would work on that size of values in every part of the datapath (eg 32-bit adders, 32-bit bitwise boolean...)
• SERV serializes all operations, trading speed for area – perform 1-bit addition 32 times

20

2023-10-12

SERV

And yes, SERV does play Doom, albeit extremely slowly... Though unfortunately not on our particular chip.

21

2023-10-12

Our version: Subservient

• SubSERVient to the management processor...
• Keeps register file and main memory in the same SRAM
• The management processor can halt SERV, at which point a mux gives the management processor access to SERVs memory over the Wishbone bus
• That is: we can program SERV and observe results from the management processor

22

2023-10-12

Success!

• Basic Openlane support �is merged into Edalize
• Two tape-outs of SERV,�one delivered
• Verification done using�Icarus Verilog simulator,�also open source

23

2023-10-12

Success! But...

• Haven't managed to fully�bring up chip from first tapeout
• Known production issue in�that fabrication run, so still�hopes for the second �tapeout

24

2023-10-12

Success! But...

• OpenRAM compiler was immature
• Our design had extremely�large area due to using �flipflops for memory
• About 1000x1000 micrometers,�25 MHz clock frequency

25

2023-10-12

Success! But...

• Current support minimalistic
• Creating full chip through�one Fusesoc command�would require more work
• For example generating�non-digital parts such as�pad frame

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2023-10-12