Programming 8251 USART Controller

Dr A Sahu

Dept of Comp Sc & Engg.

IIT Guwahati

Hierarchy of I/O Control Devices

8155

I/O + Timer

8255

I/O

8253/54

Timer

2 Port (A,B),

No Bidirectional

HS mode (C)

4 mode timer

2 Port (A,B)

A is Bidirectional

HS mode (C)

Extra controls

6 mode timer

8259

Interrupt controller

8237

DMA controller

8251

Serial I/O USART controller

Outline

• Asynchronous Communication
• 8251 USART Architecture
• USART Registers
• Programming UART
• RS 232 Port
• Interfacing CRT Monitor using a UART and RS-232 port

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Data Comm: Serial Vs Parallel

• Serial
• Cheaper
• Slower
• Parallel
• Faster
• Data skew
• Limited to small distances

Type of Serial Communication

Sender

Sender

Receiver

Receiver

Data

Data

Data

Data

Data

Data

Data

Data

a

Transmission Gaps

Asynchronous transmission

Synchronous transmission

CLK

Framing in Asynchronous

• Character oriented
• Each character carried start bit and stop bits
• When No data are being transmitted
• Receiver stay at logic 1 called mark, logic 0 is Space
• Framing:
• Transmission begins with one start bit (low/0)
• Followed by DATA (8bit) and
• Stop bits (1 or 2 bits of logic high)

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Type of Serial Communication

Asynchronous transmission

8 bit Data

Start Bit

Start Bits

1 0 0 0 1 1 1 0

LSB MSB

Time

1 start

bit

1 or 2 Stop

bit

Source data

8085 Serial I/O lines

• Serial Input Data (SID)
• Serial Output Data (SOD)
• Instruction SIM is necessary to output data
• Interpretations (ACC contents)

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MVI A, 80 ; Set D₇ in the ACC=1

RAR ;Set D₆ =1 and bring carry into D₇

SIM ; output D₇

Data transmission Program on SOD

• Transmit an ASCII Char stored in Register B

MVI B ASCIIDatabyte ; get data byte in B

MVI C,0BH ; set up counter for 11 bits

XRA A ; reset carry to 0

NXTbit: MVI A,80H ;set D7=1 in ACC

RAR ;bring Carry in D7 and set D6=1

SIM ;output D7

CALL DELAYBittime ;wait for fixed time (BWT)

STC ;set Carry 1

MOV A,B ;Place ASIII car in acc

RAR ; place ASCII D0 in Carry

;and shift 1 in D7

MOV B,A ;Save B

DCR C

JNZ NXTbit

RET

Hardware control Serial I/O

• Programmable chip 8251
• Requirement of HW control serial I/O
• An input/output port are required for interfacing
• Converts data bits in to Parallel to serial & vice versa
• Data transfer to be synchronized between I/O
• USART (Universal Synchronous Asynchronous Receiver and Transmitter )

UART/USART

• Writing a program compatible with all different serial communication protocols is difficult and it is an inefficient use of microprocessor.
• UART: Universal Asynchronous Receiver/Transmitter chip.
• USART: Universal Synchronous/Asynchronous Receiver/Transmitter chip.
• The microprocessor sends/receives the data to the UART in parallel, while with I/O, the UART transmits/receive data serially.
• 8251 functions are integrated into standard PC interface chip.

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UART / CPU interface

CPU

8251

status

(8 bit)

data

(8 bit)

serial

port

xmit/

rcv

• UART/USART
• 8251 USART
• 8250/16450 UART is a newer version of 8251.
• 16550 is the latest version UART.

8251 Block Diagram

Data Bus

Buffer

Transmit

Buffer

Receive

Buffer

Transmit

Control

Receive

Control

R/W

Control

Logic

Modem Control

Internal

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Line

D7-D0

RESET

CLK

C/D^b

RD^b

WR^b

CS^b

DSR^b

DTR^b

CTS^b

RTS^b

TXD

TXRDY

TXE

TXC

RXD

RXRDY

RXC

SYBDET/BD

8251 Registers

Control Logic & Registers

R/W

Control

Logic

RESET

CLK

C/D^b

RD^b

WR^b

CS^b

Data Buffer register

D7-D0

C/D^b=0

RD^b or WR^b

Control Register

16 bit

Status Register

8 bit

C/D^b=1

WR^b=0

C/D^b=1

RD^b=0

Internal

Data

​

Bus

Transmitter

Receiver

Transmitter and Receiver

Data

Buffer

Register

D0

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D7

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Internal

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Data

Bus

Transmitter

Buffer

Register

Receiver

Buffer

Register

Out put

Register

Input

Register

Transmitter

Control Logic

Receiver

Control Logic

TxD

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TxC^b

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TxRDY

TxE

RxD

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RxC^b

RxRDY

8251: Command Register

(Mode word format)

D7

D6

D5

D4

D3

D2

D1

D0

Framing Control

# of Stop bits

00: invalid

01: 1 bit

10: 1.5 bits

11: 2 bits

Parity Control

X0=No Parity

01: Even

11: Odd

Character length

00: 5 bits

01: 6 bits

10: 7 bits

11: 8 bits

Baud Rate

00: Syn. Mode

01: x1 clock

10: x16 clock

11: x64 clock

Command Register

(Command Word Format)

TxE: transmit enable (0/1 Enable Disable)

DTR: data terminal ready (1=ENABLE DTR)

RxE: receiver enable (1/0=EN/DISABLE)

SBPRK: send break character 1= force TxD low

ER: error reset (Reset Flags: Parity ,Over run, Framing Error of Status Word)

RTS: request to send (1= Enable Request to send)

IR: internal reset (Reset 8251 to mode)

EH: enter hunt mode (1=search for Sync Character)

8251: Status Regsiter

TxRDY transmit ready (DB Buffer is empty)

RxRDY receiver ready

TxEMPTY transmitter empty

PE parity error (1=when PE detected)

OE overrun error

FE framing error (Aynsc only, Valid stop bit not detected)

SYNDET sync. character detected

DSR data set ready (DSR set at 0 level)

RS 232 (Recommended Standard)

• RS232: Data transmitted as Voltage to terminal
• 20KBps, 50Mters only
• Improved to RS 422A (9 pine), RS 423A (15 pin-VGA)
• Modem (Data transmitted by Frequency)

Data Terminal Equipment

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(DTE)

CPU

Data Communication

Equipment

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(DCE)

I/O

2

​

​

3

​

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7

​

2

​

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3

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7

RS-232 Cable

Transmit

Transmit

Receive

Receive

+9V

-9V

+9V

-9V

+3V

-0.2V

3V

0.2V

RS-232: Mostly used for Monitor

DB-25 DB9

Interfacing a CRT monitor using RS-232 terminal using 8251

• Connect a RS 232 port onto a CRT terminal
• Address the 8251A USART at FF to control transmission
• Specify initialization instructions and status word to transmit characters
• Async mode with 9600 buad
• Character length= 7 bit + 2 stop bit
• No parity check
• Write instruction to initialize USART and read status word and Setup a loop until the transmitter is ready

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Interface Diagram

8251A

TxD

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RxD

RxC^b

TxC^b

CLK

CTS^b GND

8085

MPU

D7

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D0

CS^b

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C/D^b

A7

A1

A0

Voltage Converter

IOR^b

IOW^b

Reset Out

CLK Out

RD^b

WR^b

RESET

CLK

D7

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D0

Control & Status Register Address=FFH

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C/D^b line should be high, == > A₀ =1

Initialization of UART

Mode

Word

COMMAND WORD

STATUS

CAH

11H

01H

Initialization instructions

SETUP: MVI A,CAH ; load mode word

OUT FFH ;Write mode word in control register

MVI A,11H ; load command word to enable TX

OUT FFH ;Enable the transmitter

STATUS: IN FFH ; Read the status register

ANI 01H ; Mask all bit except D0

JZ STATUS ; if D0=0 the TX buffer if full

Display message stored at memory location 2070 to CRT

Message is “HELLO CS421”

2070. 0E ; 13 characters to follow
2071. 48; Letter H
2072. 45; Letter E
2073. 4C; Letter L
2074. 4C ; Letter L
2075. 4F ; Letter H
2076. 20; space
2077. 43; Letter C
2078. 53; Letter S
2079. 34; Digit 4
2080. 32;Digit 2
2081. 31; Digit 1
2082. 0D; Carriage return
2083. 0A; Linefeed

Write a program to display message at CRT terminal

LXI H 2070H ; Meory ptr for Message

MOV C, M ; Set up Ctr register

MVI A,40; Reset 8251

OUT FFH

MVI A,CA; Initialize 82512

OUT FFH

MVI A,11 ; initialize for transmit

OUT FFH

STATUS: IN FFH

ANI 01H ;Ckeck TxRDY

JZ STATUS ; is txRDY 1 ? If not wait

INX H ; Pont to Next Char

MOV A,M ; place the Char in ACC

OUT FEH ; Send the Char to Transmitter

DCR C ; DCr cnt

JNZ STATUS ;Again Send the rest of Char

HLT

Thanks