1 of 10

ALU

IMem Rd

RF Rd

+

pend. replay PC

RF Wr

ld rtn

br. target

+

Dec

PC

pend

+1

@rslt

@wb

@exe

@rd

@tgt

@dec

@fet

@pc

ld data

1-Stage

DMem Rd/Wr

@pc

@rslt

(into @rd)

2 of 10

ALU

IMem Rd

RF Rd

+

pend. replay PC

reg. byp.

RF Wr

ld rtn

br. target

+

Dec

PC

pend

+1

@rslt

@wb

@exe

@rd

@tgt

@dec

@fet

@pc

ld data

Retimed 4-Stage

DMem Rd/Wr

@pc

@rslt

(into @rd)

3 of 10

ALU

IMem Rd

RF Rd

+

pend. replay PC

reg. byp.

RF Wr

ld rtn

br. target

+

Dec

PC

pend

+1

@rslt

@wb

@exe

@rd

@tgt

@dec

@fet

@pc

ld data

4-Stage

DMem Rd/Wr

@pc

@rslt

(into @rd)

4 of 10

ALU

IMem Rd

RF Rd

+

pend. replay PC

reg. byp.

RF Wr

ld rtn

br. target

+

Dec

PC

pend

+1

@rslt

@wb

@exe

@rd

@tgt

@dec

@fet

@pc

ld data

6-Stage

DMem Rd/Wr

@pc

@rslt

(into @rd)

5 of 10

ALU

IMem Rd

DMem Rd/Wr

RF Rd

+

pend. replay PC

reg. byp.

RF Wr

ld rtn

br. target

+

Dec

PC

pend

+1

@rslt

@wb

@exe

@rd

@tgt

@dec

@fet

@pc

DMem Rd/Wr

ld rtn

6 of 10

ALU

RF Rd

+

pend. replay PC

reg. byp.

RF Wr

br. target

+

Dec

PC

pend

+1

< >

IMem Rd

7 of 10

ALU

IMem Rd

DMem Rd/Wr

RF Rd

+

pend. replay PC

reg. byp.

RF Wr

ld rtn

br. target

+

Dec

PC

pend

+1

@rslt

@wb

@exe

@rd

@tgt

@dec

@fet

@pc

DMem Rd/Wr

riscv-

formal

ld rtn

8 of 10

ALU

IMem Rd

DMem Rd/Wr

RF Rd

+

pend. replay PC

reg. byp.

RF Wr

ld rtn

br. target

$ld_data

+

Dec

PC

pend

+1

@rslt

@wb

@exe

@rd

@tgt

@dec

@fet

@pc

DMem Rd/Wr

riscv-

formal

ld rtn

$ld_data

$dest_reg

$dest_reg

9 of 10

Dec Exe WB

“Swiss Cheese” CPU

Config

ISA = ...

BrPred = ...

...

Params

WordWidth = ...

MemSize = …

...

Staging

Fetch = 1

Decode = 2

Execute = 3

...

BrPred

Dec Exe WB

TL-Verilog

Verilog

ISA

WARP-V Source

10 of 10

RISC-V

🗸