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VLSI Design-�unit 5

DR.P.SUVEETHA DHANASELVAM

ASSOCIATE PROFESSOR/ECE

VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY,

MADURAI.

DR.P.SUVEETHA DHANASELVAM

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IMPLEMENTATION STRATEGIES AND TESTING �

FPGA Building Block Architectures, FPGA Interconnect Routing Procedures. Design for Testability: Ad Hoc Testing, Scan Design, BIST, IDDQ Testing, Design for Manufacturability, Boundary Scan.

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FPGA Outline

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FPGA

  • Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure:

1. the interconnection between the logic blocks,

2. the function of each block.

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Simplified version of FPGA internal architecture:

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Gate Array Technology �(IBM - 1970s)

  • Simple logic gates
    • combine transistors to�implement combinational�and sequential logic
  • Interconnect
    • wires to connect inputs and�outputs to logic blocks
  • I/O blocks
    • special blocks at periphery�for external connections
  • Add wires to make connections
    • done when chip is fabbed
      • “mask-programmable”
    • construct any circuit

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Field-Programmable Gate Arrays

  • Logic blocks
    • to implement combinational�and sequential logic
  • Interconnect
    • wires to connect inputs and�outputs to logic blocks
  • I/O blocks
    • special logic blocks at periphery�of device for external connections�

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FPGA Building Block Architecture

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CLB-Configurable Logic Blocks

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FPGA Interconnect Routing Procedures

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Adhoc Testing

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Example

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IDDQ Testing

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IDDQ Testing

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IDDQ testing

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Thank You

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Design for Testability

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