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RISC: Reduced Instruction Set Computer

A 32-bit microprocessor designed to run C and UNIX

(a.k.a. RISC-I and RISC-II)�David Patterson and Carlo Sequin

The Idea and The Challenge

1980 - 1984

The RISC Group

RISC-I was developed in a series of 4 graduate classes. RISC-II was designed later by Katevenis and Sherburne. 1st row: Korbin Van Dyke, Osamu Tomisawa (Mitsubishi), Jim Peek, David Patterson (Berkeley), Carlo Sequin (Berkeley), Peter Kessler (Google), John Foderaro (Franz Inc). 2nd row: Bob Sherburne, John Ousterhout (Stanford), Ralph Campbell, Rich Piepho, Helen Davis, Dan Fitzpatrick, Dan Halpern. 3rd row: Manolis Katevenis (U. Crete), Bob Cmelik, Robert Hyerle, Paul Hansen, Mike Shebanow, Scott Baden (UCSD), Howard Landman. Not pictured: Zvi Peshkesh

Direct Impact

The trend in instruction set architecture (ISA) was leading to ever increasing complexity. Could a new, very simple but judiciously chosen ISA lead to smaller and faster circuits, thus yielding overall higher performance? We set out to prove that a VLSI computer would be better implemented as a �Reduced Instruction Set Computer (RISC) than as a Complex Instruction Set Computer (CISC).

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RISC microprocessor

• The Berkeley RISC papers influenced the design of the Acorn RISC Machine (ARM, later rebranded Advanced RISC Machine).
• 98% of processors shipped in 2014 were RISC (ARM 12.0B, Tensilica 2.0B, �ARC 1.5B, MIPS 0.8B) v. 2% CISC (x86 0.4B).
• The National Academy includes RISC among federally funded academic research projects that have led to multibillion dollar industries.
• Still widespread agreement in 2016 that RISC principles are best for a general purpose ISA.

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Technical Approach

Selected Publications

• Patterson, D. A., & Ditzel, D. R. The Case for the Reduced Instruction Set Computer. ACM SIGARCH Computer Architecture News, 8(6), 1980.
• Clark, D. W., & Strecker, W. D. Comments on “The Case for the Reduced Instruction Set Computer.” ACM SIGARCH Computer Architecture News, 8(6), 1980.
• Patterson, D. A., & Sequin, C. H. RISC I: A Reduced Instruction Set VLSI Computer. Proc. ISCA, 1982. Also reprinted in 25 years of the International Symposia on Computer Architecture, 1998.
• Katevenis, M. Reduced Instruction Set Computer Architectures for VLSI, MIT Press, 1985.

RISC-I was built in 5 micron NMOS using 44,420 transistors with a die area of 77 mm², and ran at 1 MHz. RISC-II ran at 3 MHz in 3 micron NMOS using 40,760 transistors and a die area of 60 mm².

Indirect Impact

• RISC-I and RISC-II were the basis of the SPARC ISA from Sun Microsystems (now Oracle). These computers power most financial services, which a billion people use each day.
• Manolis Katevenis won �the 1984 ACM Doctoral �Dissertation Award.
• IEEE installed a plaque at Berkeley in 2015 �recognizing RISC-I as the�first RISC microprocessor.

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(1982 RISC talk slides - cars by Linda Patterson)

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