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Configuration

Architectural clock gating (disable the parts of the chip when not in use - for power saving)
Little Endian bus access – Simplifying memory access (LSB to lowest address)

Four Breakpoints
Debug support (via 2-wire debug pins SWD/SWCLK)
IOPORT: This is a dedicated interface for communicating with local peripherals, such as timers, ADC, and DAC.
32-bit instruction fetch (to match 32-bit data bus)

IOPORT:

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Configuration

26 interrupts
8 MPU regions

(Memory Protection Unit) regions allow the microcontroller to protect different areas of memory from unauthorized access

All registers reset on powerup (to know the status on boot up
Fast multiplier (hardware)
SysTick timer (precise timekeeping mechanism)
Vector Table Offset Register (This register specifies the location of the interrupt vector table)
34 WIC (Wake-up Interrupt Controller)
DAP (Debug Access Port, which provides a standardized interface for debugging and programming the microcontroller.)

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Functional Description

32-bit RISC processor

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• The ARMv6-M Thumb® instruction set.

• Thumb-2 technology.

• An ARMv6-M compliant 24-bit SysTick timer.

• A 32-bit hardware multiplier. This is the standard single-cycle multiplier

• The ability to have deterministic, fixed-latency, interrupt handling.

• Load/store multiple instructions that can be abandoned and restarted to facilitate rapid interrupt handling.

• C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (CABI) compliant exception model that enables the use of pure C functions as interrupt handlers.

• Low power sleep-mode entry us

Features

The ARMv6-M Thumb® Instruction Set: The ARMv6-M Thumb instruction set refers to the 16-bit instruction set architecture used by the ARM Cortex-M0+ processor. It's designed to be more code-efficient compared to the full 32-bit ARM instruction set. Instructions in the Thumb instruction set are shorter, allowing for more instructions to fit in memory and reducing code size.
Thumb-2 Technology: Thumb-2 is an enhancement to the original Thumb instruction set. It allows for a mixture of both 16-bit and 32-bit instructions, providing a balance between code density and performance. Thumb-2 technology provides improved code density, better performance due to more flexible instructions, and support for advanced features.
ARMv6-M Compliant 24-bit SysTick Timer: The SysTick timer is a system timer available in Cortex-M processors. In this case, the ARMv6-M compliant 24-bit SysTick timer refers to a timer that can generate periodic interrupts at a specified interval. It's commonly used for creating real-time operating system (RTOS) tick interrupts and other timing-related functions.
32-bit Hardware Multiplier: The Cortex-M0+ microcontroller includes a 32-bit hardware multiplier, which allows for efficient multiplication operations to be performed in a single clock cycle. This is particularly beneficial for signal processing and mathematical calculations.
Deterministic, Fixed-latency Interrupt Handling: This feature ensures that the interrupt handling mechanism in the Cortex-M0+ has a consistent and predictable latency, meaning that the time taken from an interrupt request to the execution of the corresponding interrupt handler is fixed and known. This is crucial for real-time systems where timing precision is important.
Load/Store Multiple Instructions for Rapid Interrupt Handling: Load/store multiple instructions are used to efficiently save and restore multiple registers during an interrupt service routine. The Cortex-M0+ supports a unique feature where load/store multiple instructions can be abandoned if an interrupt occurs during their execution, and then resumed later. This helps in minimizing interrupt latency and maintaining real-time responsiveness.
C Application Binary Interface (CABI) Compliant Exception Model: The CABI-compliant exception model enables C functions to be used as interrupt handlers. This makes it easier to write and manage interrupt service routines in C language, rather than using assembly language. The Cortex-M0+ architecture provides a well-defined interface for passing parameters and handling exceptions in C.
Low Power Sleep-Mode Entry: The Cortex-M0+ processor supports various low-power modes where it can significantly reduce power consumption while still being able to wake up quickly when needed. Sleep-mode entry refers to the ability of the processor to transition into a low-power state efficiently to save energy.

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The Nested Vectored Interrupt Controller (NVIC) features are:

• 26 external interrupt inputs, each with four levels of priority.

• Dedicated Non-Maskable Interrupt (NMI) input (which can be driven from any standard interrupt source)

• Support for both level-sensitive and pulse-sensitive interrupt lines.

• Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support. • Relocatable vector table.

NVIC features

26 External Interrupt Inputs with Four Levels of Priority: The NVIC allows the microcontroller to handle external interrupts coming from various sources. In the case of the Cortex-M0+, there are 26 external interrupt inputs available. Each of these interrupts can have one of four priority levels assigned to it. This prioritization helps the microcontroller decide which interrupt to process first when multiple interrupts occur simultaneously.
Dedicated Non-Maskable Interrupt (NMI) Input: The NMI is an important type of interrupt that has a higher priority than other regular interrupts. It is typically reserved for critical events that require immediate attention, even if other interrupts are being serviced. The NMI input can be driven from any standard interrupt source, allowing for flexibility in designating critical events that can't be masked or delayed.
Support for Level-Sensitive and Pulse-Sensitive Interrupt Lines: Level-sensitive interrupts remain active as long as the interrupt condition persists. Pulse-sensitive interrupts trigger on a specific edge (rising or falling) of the interrupt signal and do not require a continuous condition. This flexibility allows the NVIC to handle interrupts that can be either level-based or triggered by edges.
Wake-Up Interrupt Controller (WIC) for Ultra-Low Power Sleep Mode: The Wake-Up Interrupt Controller (WIC) is responsible for managing interrupts that can wake the microcontroller from low-power sleep modes. It enables the microcontroller to enter ultra-low power states while still being responsive to specific events that necessitate waking up. This feature is crucial for conserving energy in battery-powered or energy-efficient applications.
Relocatable Vector Table: The vector table contains the addresses of interrupt service routines (ISRs) for each interrupt source. In the NVIC of the Cortex-M0+, the vector table is relocatable, meaning it can be placed at different memory addresses in the microcontroller's memory. This provides flexibility in memory layout and allows the microcontroller to boot from different locations in memory, facilitating bootloader and application separation.

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An IR sensor is connected to the RP2040 in GPIO7, find the address and the value to be given at the address to enable the GPIO7 as the input pin.
30 LEDs are connected across the GPIOs, find the address to turn on all the LED and write the value to be given

SIO

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NVIC

Intended Learning Outcome

How and what registers are used in NVIC

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NVIC

External interrupt signals connect to the Nested Vectored Interrupt Controller (NVIC), and the NVIC prioritizes the interrupts.

Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts

All NVIC registers are only accessible using word transfers. Any attempt to read or write a halfword or byte individually is unpredictable.

“Nested" refers to the fact that interrupts can themselves be interrupted, by higher-priority interrupts. "Vectored" refers to the hardware dispatching each interrupt to a distinct handler routine

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SysTick timer

• A 24-bit system timer (SysTick).

• Additional configurable priority SysTick interrupt.

Low power modes

The implementation includes a WIC (Wakeup Interrupt Controller). This enables the processor and NVIC to be put into a very low-power sleep mode leaving the WIC to identify and prioritize interrupts.

The processor fully implements the Wait For Interrupt (WFI), Wait For Event (WFE) and the Send Event (SEV) instructions. In addition, the processor also supports the use of SLEEPONEXIT, that causes the processor core to enter sleep mode when it returns from an exception handler to Thread mode.

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NVIC register summary

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Lets talk about memory

the "0" in the last position indicates that there is no onboard non-volatile flash memory, but it still includes the 16 KB ROM for essential functions.

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Total SRAM: 264 KB

Total ROM: 16 KB.

XIP Flash Memory: Typically up to 16 MB, though dependent on external flash.

SRAM: 264 KB

There are four 16k x 32-bit banks (64kB each) and two 1k x 32-bit banks (4kB each).

Striped (interleaved) SRAM0-SRAM3 (higher performance due to faster memory access).
Non-striped SRAM4-SRAM5 (sequential access).

Memory

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Address Map

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MPU

Intended Learning Outcome

How and what registers are used in MPU

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• Eight user-configurable memory regions.

• Eight sub-region disables per region.

• Execute never (XN) support.

• Default memory map support.

MPU features

Eight User-Configurable Memory Regions: In an ARM Cortex-M microcontroller, the memory protection unit (MPU) allows you to divide the memory space into multiple regions and define access permissions for each region. The MPU can define up to eight distinct memory regions, each with its own set of attributes like access permissions (read, write, execute) and memory attributes (cacheable, bufferable, etc.). This allows you to control and restrict access to different parts of memory, which can be particularly useful in ensuring the security and integrity of critical data or code.
Eight Sub-Region Disables Per Region: Each of the eight memory regions can be further divided into multiple sub-regions. These sub-regions can be selectively enabled or disabled. Disabling a sub-region prevents any access to that specific sub-region, providing a finer level of control over memory protection. This is beneficial when you want to allow certain parts of a memory region to be accessible while protecting other parts from unwanted access.
Execute Never (XN) Support: The "Execute Never" (XN) feature is a security measure that prevents code execution from certain memory regions. This is a crucial security feature that helps protect against code injection attacks. By marking a memory region as "Execute Never," you ensure that no instructions within that region can be executed as code. This prevents malicious code from being executed from areas of memory where it shouldn't be present, enhancing the overall security of the system.
Default Memory Map Support: The "Default memory map support" typically refers to the concept of having a default memory region where memory regions not explicitly defined in the MPU configuration are placed. This allows you to ensure that any memory region not specified in the MPU configuration is still subject to some level of access control. This can be useful in maintaining a secure system even if you haven't explicitly defined permissions for all memory regions.

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DEBUG

Intended Learning Outcome

Debug How to set different debugging in RP2040 using their registers

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• Four hardware breakpoints.

• Two watchpoints.

• Program Counter Sampling Register (PCSR) for non-intrusive code profiling.

• Single step and vector catch capabilities.

• Support for unlimited software breakpoints using BKPT instruction.

• Non-intrusive access to core peripherals and zero-waitstate system slaves through a compact bus matrix. A debugger can access these devices, including memory, even when the processor is running.

• Full access to core registers when the processor is halted.

• Core Sight compliant debug access through a Debug Access Port (DAP) supporting Serial Wire debug connections.

Debug features

Four Hardware Breakpoints: Hardware breakpoints allow you to pause program execution at specific memory addresses. You can set up to four breakpoints, which are points where the processor will automatically halt when the program reaches them. This is extremely useful for pinpointing issues in your code and understanding program behavior.
Two Watchpoints: Watchpoints are similar to breakpoints but are triggered by memory access rather than specific instruction addresses. You can set two watchpoints to monitor memory locations for read, write, or read-write accesses. When a watchpoint condition is met, the processor halts, allowing you to investigate memory-related issues.
Program Counter Sampling Register (PCSR): The Program Counter Sampling Register is used for non-intrusive code profiling. It allows you to gather information about where the processor is spending its time in your code without causing significant disruption. This is valuable for optimizing code performance.
Single Step and Vector Catch Capabilities: Single stepping allows you to execute your program one instruction at a time, making it easier to understand how the code flows and to identify issues. Vector catch capabilities enable the debugger to halt execution when certain system events, such as interrupts or exceptions, occur.
Unlimited Software Breakpoints: The processor supports software breakpoints set using the BKPT (Breakpoint) instruction. These breakpoints are inserted directly into the code and can be used without any dedicated hardware resources.
Non-Intrusive Access to Core Peripherals: The compact bus matrix provides a way for the debugger to access core peripherals and memory without significantly disrupting the processor's operation. This allows you to inspect memory contents, peripheral registers, and other information while the processor is running.
Full Access to Core Registers: When the processor is halted (stopped for debugging), you have complete access to its core registers. This enables you to examine the internal state of the processor, such as the values of registers, flags, and other critical information.
Core Sight Compliant Debug Access: The Core Sight Debug Access Port (DAP) is a standardized interface that supports Serial Wire Debug (SWD) connections. This interface allows a debugger to communicate with the processor for debugging and profiling purposes. It's a standard way to access debugging features across different ARM processors.

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The processor is implemented with a low gate count Debug Access Port (DAP). The low gate count Debug Access Port (DAP) provides a Serial Wire debug-port, and connects to the processor slave port to provide full system-level debug access.

Debug Access Port

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DMA

Direct Memory Access

DMA:

Data requests,
Interrupts and
Memory

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The RP2040 Direct Memory Access (DMA) controller has separate read and write master connections to the bus fabric, and performs bulk data transfers on a processor’s behalf. This leaves processors free to attend to other tasks, or enter low-power sleep states.

Direct Memory Access

Intended Learning Outcome

Illustrate Direct Memory Access

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Direct Memory Access

32 bits in size, one read access and one write access every clock cycle

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• Memory-to-peripheral: a peripheral signals the DMA when it needs more data to transmit. The DMA reads data from an array in RAM or flash, and writes to the peripheral’s data FIFO.

• Peripheral-to-memory: a peripheral signals the DMA when it has received data. The DMA reads this data from the peripheral’s data FIFO, and writes it to an array in RAM.

• Memory-to-memory: the DMA transfers data between two buffers in RAM, as fast as possible

There are 12 independent channels, each which supervise a sequence of bus transfers, usually in one of the following scenarios:

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Direct Memory Access

CONTROL AND STATUS REGISTERS

TRANSFER SIZE CAN BE EITHER 32, 16, OR 8 BITS

CHAIN_TO

Making the DMA more autonomous means that much less processor supervision is required: overall this allows the system to do more at once, or to dissipate less power.

We do all these to :

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Configuring Channels

Each channel has four control/status registers

• READ_ADDR is a pointer to the next address to be read

• WRITE_ADDR is a pointer to the next address to be written to

• TRANS_COUNT shows the number of transfers remaining in the current transfer sequence,

• CTRL is used to configure all other aspects of the channel’s behaviour, to enable/disable it, and to check for completion.

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Configuring Channels

Read and Write Addresses

READ_ADDR and WRITE_ADDR contain the address the channel will next read from, and write to, respectively. (update automatically, increment by 1, 2 or 4 bytes at a time)
Software should generally program these registers with new start addresses each time a new transfer sequence starts. If READ_ADDR and WRITE_ADDR are not reprogrammed, the DMA will use the current values as start addresses for the next transfer.

For example:

• If the address does not increment (e.g. it is the address of a peripheral FIFO), and the next transfer sequence is to/from that same address, there is no need to write to the register again.

• When transferring to/from a consecutive series of buffers in memory (e.g. scattering and gathering), an address register will already have incremented to the start of the next buffer at the completion of a transfer.

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Configuring Channels

Transfer Count

Reading from TRANS_COUNT yields the number of transfers remaining in the current transfer sequence
Each time the channel starts a new transfer sequence, the most recent value written to TRANS_COUNT
For debugging purposes, the last value written can be read from the DBG_TCR
If the channel is triggered multiple times without intervening writes to TRANS_COUNT, it performs the same number of transfers each time.

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Configuring Channels

Control/Status

Configure the size - CTRL.DATA_SIZE
Configure if and how read and write - CTRL.INCR_WRITE, CTRL.INCR_READ, CTRL.RING_SEL, CTRL.RING_SIZE
Another channel (or none) to be triggered - CTRL.CHAIN_TO
Peripheral data request (DREQ) signal - CTRL.TREQ_SEL
See when the channel is idle - CTRL.BUSY
Channel has encountered a bus error - CTRL.AHB_ERROR, CTRL.READ_ERROR, or CTRL.WRITE_ERROR

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Starting Channels

3 ways to start a channel

Writing to a channel trigger register
A chain trigger from another channel which has just completed, and has its CHAIN_TO field configured
The MULTI_CHAN_TRIGGER register, which can start multiple channels at once

Aliases and Triggers

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The channel is disabled via CTRL.EN
The channel is already running
The value 0 is written to the trigger register

Starting Channels

Trigger registers do not start the channel if

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Starting Channels

Chaining

When a channel completes, it can name a different channel to immediately be triggered. This can be used as a callback for the second channel to reconfigure and restart the first.

"ping-pong" configuration

This feature is configured through the CHAIN_TO field in the channel CTRL register.

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Starting Channels

Null Triggers and Chain Interrupts

writing all-zeroes to a trigger register does not start the channel. This is called a null trigger, and it has two purposes:

Cause a halt at the end of an array of control blocks, by appending an all-zeroes block
Reduce the number of interrupts generated when control blocks are used

By default, a channel will generate an interrupt each time it finishes a transfer sequence, unless that channel’s IRQ is masked in INTE0 or INTE1

The channel CTRL register has a field called IRQ_QUIET

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Data Request (DREQ)

Peripherals produce or consume data at their own pace. If the DMA simply transferred data as fast as possible, loss or corruption of data would ensue. DREQs are a communication channel between peripherals and the DMA, which enables the DMA to pace transfers according to the needs of the peripheral.

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Data Request (DREQ)

Use of DREQ in DMA

Intended Learning Outcome

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Credit-based DREQ Scheme

The RP2040 DMA is designed for systems where:

The area and power cost of large peripheral data FIFOs is prohibitive

The bandwidth demands of individual peripherals may be high, e.g. >50% bus injection rate for short periods

Bus latency is low, but multiple masters may be competing for bus access

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Direct Memory Access

Addressing ‘em

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Direct Memory Access

Configure ‘em

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Sniff Hardware

Sniff hardware is a generic term used to describe a piece of hardware or a component in a computer system that is capable of observing, monitoring, or interacting with data transfers on specific channels or buses.

A checksum is a mathematical value calculated from the data to check for errors or verify data integrity. The statement suggests that the sniff hardware may be involved in the calculation or monitoring of this checksum as data is transferred

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In A DMA device, what value should I write to the control and status register and at which address,

If:

The DMA device is connected to channel 2
There is a write error
The bus is busy
Sniff is enabled
Half word swap is demanded
Interrupt is set to be in quiet mode
Transfer request is from UART0_Tx

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In A DMA device, what value should I write to the control and status register and at which address,

If:

Set chain to be in ping pong configuration with channel 4
No ring configuration
The operation is between a i2c and memory device.
16bit data is transferred
I2c device connected must be given the top priority

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In A DMA device, what value should I write to the control and status register and at which address,

If:

The DMA device is connected to channel 4
There is a read error
The bus is not busy
Sniff is enabled
Half word swap is demanded
Interrupt is set to be in quiet mode
Transfer request is from UART0_Tx

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In A DMA device, what value should I write to the control and status register and at which address,

If:

Set chain to be in ping pong configuration with channel 1
No ring configuration
The operation is between a i2c and memory device.
16bit data is transferred
I2c device connected must be given the priority next to the power interrupt

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1	0	1	x	x	x	x	1	1	0	0	1	1	1	1	1	0	0	1	0	0	x	x	x	x	x	1	0	1	0	1	1

The DMA registers start at a base address of 0x50000000

CH2_CTRL_TRIG

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

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