A gm/Id based approach to design High Gain Folded Cascode Amplifier

Animesh Sharma (MT20317)

Shakti Shrey (MT20323)

Contents:

• Folded Cascode Circuit
• Design Approach using Square-Law
• Deviation around the Square Law
• gm/Id Approach and models
• Choice of gm/Id in design
• Design using gm/id approach : Generic Design Flow
• gm/Id Implementation on Folded Cascode Design.
• Comparative Analysis of Results Achieved
• Challenges faced & Solutions
• References

Design Specifications :

Design Approach using Square-Law

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Decide the Total current from Power constraint and supply voltage available

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Budget current in every Branch

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Allocating V_ov across all transistors according to currents budgeted across them

�Apply square-Law to find aspect ratio across every Tx.�I_ds= K(W/L)V_ov²

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Decide V_bias according to allocated V_ov

Perform Simulations

Specifications met?

Design Complete

Change V_ov using different W/L

No

Yes

Subject Circuit : The Classical Square Law approach

• It is composed of p-channel differential input pair (M1, M2), followed by common-gate stages (M7, M8) and current sources (M5, M6), and a self-biased cascode current mirror (M9 – M12) that inverts the current signal. M3 and M4 form a current mirror that provides bias current for differential input pair.

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• Iref =40uA�Ib = Ia + Iref/2�Ib > Iref/2 => Ia=10uA, Ib=30uA�
• After this Vov distribution, and implying square law, to find bias voltages�
• Vb1 = 860 mV and Vb2= 620mV, (taking Vtn=470mV & Vtp=450mV)

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> Single stage Folded Cascode Op-Amp

Arrived Design Sizings using Square law

Results Achieved using Square Law :

Gain = 73 dB Phase Margin = 57 deg UGB = 8.64 MHz

PSRR = 78.067 dB

Ad = 73.55 dB Acm = -14.86 dB CMRR = Ad - Acm = 88.41 dB

Slew Rate = 3V/usec

Deviation around the Classical Square Law!

• The actual current does not drops to zero for Vgs < Vt.
• The Square law does not take into account of Vt variation with respect to Vds or L.

Thus, it is a challenging task to fix V(ON) = Vgs - Vt.

• The Square law fails miserably at predicting gm/Id in moderate & Weak Inversion regions.

Classical Square Law Vs. Simulation Models Approach

• Since there is a disconnect between actual transistor behavior and the simple square law model, the Square-law driven design optimization will be far off from actual Simulator results.
• Strategy – Design using look-up tables or charts.

Motivation of gm/Id : We must pay I_Q to buy gm

• gm/Id is measure of the efficiency to translate Current (i.e. power) into gm (gain).
• Higher gm/Id translates to better gain and better Power efficiency.

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• gm/Id is strongly related to the performance of analog circuits.
• It also gives an indication of the device operating region.
• It can be used for transistor sizing.

Characterisation of gm/Id : nMOS

• Obtain models through a DC sweep simulation of the transistor models.
• Tabulate the figures of merit considering gm/ID as an index, over a reasonable range of gm/Id --
• Transit frequency (fT)
• Intrinsic gain (gm/gds)
• Repeat the sweep for different lengths --- 180nm, 200 nm, …..
• In order to compute device widths, we need one more table that links gm/ID and current density ID/W.

Effect of gm/Id : Region of Operation

Plot-1: gm/Id Vs. V-ov

Plot-2: gm/gds Vs. gm/Id

Plot-3: fT Vs. gm/Id

Plot-4: fT*(gm/gds) Vs. gm/Id

Id/W Vs gm/Id across different L: Sizing of devices

gm/Id Characterisation : pMOS

Plot-1: gm/Id Vs. V-ov Plot-2: gm/gds Vs. gm/Id

Plot-3: fT Vs. gm/Id Plot-4: fT*(gm/gds) Vs. gm/Id

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gm/Id vs Id/W : Operating region

Choice of gm/Id in the Design

Design Flow : Sizing using gm/Id technique

• We started with determining Drain Currents across each transistors by budgeting total current in our design.
• We intelligently choose gm/Id of all transistors based on their effect on our circuit.
• Based on the variation of obtained models from Virtuoso of Normalised Current (Id/(W/L)) Vs gm/Id, we determine the Normalised current values across all devices.
• Thus, we get the aspect ratio (W/L) of all devices.
• Choice of L :-
• Short Channel : High Speed (High fT)
• Long Channel : High Intrinsic gain

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gm/Id Implementation on Folded Cascode Design

Results Achieved using gm/Id:

Gain = 91dB Phase Margin = 66 deg UGB = 9.1 MHz

PSRR = 117.51 dB

Ad = 91 dB Acm = -14.86 dB CMRR = Ad - Acm = 108.115 dB

Slew Rate = 3.2 V/usec

Comparative Analysis of Results Achieved!

Challenges Faced & Solutions

• Faced difficulty while arriving at an optimized design even after several iterations.

For this we went ahead and discovered some other tuning methodologies and thus we came across gm/Id technique.

• Plotting transistor characteristic graphs w.r.t gm/Id was challenging as virtuoso tool does not inertly allow plotting graphs with derived quantities.

So, for this we had to refer to a lot of tutorials that taught how to save all the DC operational values in a file and then use them to generate required plots with the help of scripts.

• Learning Ocean scripting was challenging as it was something very new for us and we had to devote a lot of time to be able to get the desired plots.

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References

[1] F. Silveira, D. Flandre, P. Jespers, “A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA,” IEEE J. Solid-State Circuits, vol. 31, no. 9, Sept 1996, pp. 1314–1319

[2] H. Gupta, G. K. Mishra, N. Z. Rizvi, and S. K. Patnaik, “Design of high psrr folded cascode operational amplifier for ldo applications,” in 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016, pp. 4617–4621.

[3] S. L. Pinjare, G. Nithya, V. S. Nagaraja, and A. Sthuthi, “A gm/id based methodology for designing common source amplifier,” in 2018 2nd International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE), 2018, pp. 304–307.

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