Krste Asanovic

SiFive Inc.

Acting Chair

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TSC/CCM Meeting

July 3, 2024

@risc_v

Long Instruction TG Proposal

Original >32b Encoding Scheme�(Not Frozen)

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One initial proposal, 32b prefix word� (John Hauser, Andrew Waterman, Krste)

• A 48b instruction is a 32b prefix followed by 16b final element
• A 64b instruction is a 32b prefix followed by a 32b final element

RISC-V Foundation

48b (yy!=11)

64b (yyy!=111)

• 48b encoding has (3/4)*43b code space available (3/2 of original)
• 64b encoding has (7/8)*57b code space available (7/8 of original)
• Easier to parse in high-frequency, wide-issue superscalar fetch units
• Reuses most of the 16b/32b alignment logic already needed
• Extend pattern for >64b.

Byte Address

Long Instruction TG

• Create a Task Group under Unprivileged IC
• Define >32b instruction encoding schema (initially 48b and 64b)
• Define ISA extension with a few longer scalar integer instructions, e.g.,
• Load large immediates
• Load/store with large offset (especially for embedded)
• Long Jumps/JAL
• there are separate proposals for 32b longer jump encodings
• Possibly conditional branches with larger offsets
• Develop toolchain support, SAIL, ACT, Spike/QEMU

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• A non-goal to develop more specialized extensions (e.g., no 64b vector in this TG)

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Long Instruction Task Group Charter

• From the outset, the RISC-V ISA was designed to support arbitrary variable-length instructions, but to date, only 16b and 32b instructions encodings have been ratified. While a proposal for longer (>32b) instructions was presented in the original RISC-V specifications, it was deliberately not frozen at the time the base was ratified to allow the design to be revisited at a later date.

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• Longer instructions can more naturally support a larger number of standard and custom instruction-set extensions, but can also provide reduced static and dynamic code size with more efficient encodings of common instruction sequences. However, increasing the variety of instruction lengths can complicate processor front-end fetch-unit design, and the original RISC-V variable-length encoding proposal is problematic for high-performance processors with wide superscalar fetch units. This TG will evaluate alternate longer-instruction encodings and their effect on fetch-unit implementations, and propose a general encoding scheme together with an initial small set of new instructions that make use of the longer encodings to support large immediates and large branch offsets. The TG will also develop guidance on how to use the long-instruction encoding space, with a few representative examples of encodings for other types of long instructions.

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• The group will also consider the impact on toolchains, in particular, new linker relocation types that might result from new addressing modes, and evaluate the benefits of the new longer instructions in terms of static and dynamic code size, and expected performance improvements.

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RISC-V Foundation