Topic 7� Digital Circuits �Intro to Digital Electronics

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 1

ECE 271

Electronic Circuits I

Brief History of Digital Electronics

• Digital electronics can be found in many applications in the form of microprocessors, microcontrollers, PCs, DSPs, and an uncountable number of other systems.

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• The historic development of design of digital circuits:
• resistor-transistor logic (RTL)
• diode-transistor logic (DTL)
• transistor-transistor logic (TTL)
• emitter-coupled logic (ECL)
• NMOS
• complementary MOS (CMOS)

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 2

Digital Binary Logic

• Digital electronics represent signals by discrete bands of analog levels, rather than by a continuous range.

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 3

Digital Binary Logic

• Digital electronics represent signals by discrete bands of analog levels, rather than by a continuous range.

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• All levels within a band represent the same signal state.

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• Small changes to the analog signal levels due to manufacturing tolerance, or noise do not leave the discrete envelope, and as a result are ignored by signal state sensing circuitry.

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 4

Digital Binary Logic

• Digital electronics represent signals by discrete bands of analog levels, rather than by a continuous range.

​

• All levels within a band represent the same signal state.

​

• Small changes to the analog signal levels due to manufacturing tolerance, or noise do not leave the discrete envelope, and as a result are ignored by signal state sensing circuitry.

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• Binary logic is the most common style of digital logic.

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• The signal is either a 0 (low, false) or a 1 (high, true) - Positive Logic Convention

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 5

Digital Binary Logic

• Digital electronics represent signals by discrete bands of analog levels, rather than by a continuous range.

​

• All levels within a band represent the same signal state.

​

• Small changes to the analog signal levels due to manufacturing tolerance, or noise do not leave the discrete envelope, and as a result are ignored by signal state sensing circuitry.

​

• Binary logic is the most common style of digital logic.

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• The signal is either a 0 (low, false) or a 1 (high, true) - Positive Logic Convention

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• Mathematical representation of logical operations is Boolean algebra: set of operations (NOT, AND, OR, NAND, NOR, etc.) with binary or logical elements.
• To perform general logical operations, a logic family must contain NOT and at least one another function of two inputs OR or AND.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 6

Review of Boolean Algebra

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 7

NOT

Truth Table

OR

Truth Table

AND

Truth Table

NOR

Truth Table

NAND

Truth Table

Review of Boolean Algebra

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 8

NOT

Truth Table

OR

Truth Table

AND

Truth Table

NOR

Truth Table

NAND

Truth Table

Review of Boolean Algebra

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 9

NOT

Truth Table

OR

Truth Table

AND

Truth Table

NOR

Truth Table

NAND

Truth Table

Review of Boolean Algebra

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 10

NOT

Truth Table

OR

Truth Table

AND

Truth Table

NOR

Truth Table

NAND

Truth Table

Review of Boolean Algebra

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 11

NOT

Truth Table

OR

Truth Table

AND

Truth Table

NOR

Truth Table

NAND

Truth Table

Review of Boolean Algebra

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 12

NOT

Truth Table

OR

Truth Table

AND

Truth Table

NOR

Truth Table

NAND

Truth Table

 De Morgan's laws

Logic Gate Symbols and Boolean Expressions

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 13

• A logic gate is a physical model of a Boolean function: �it performs a logical operation on one or more logic inputs and produces a single logic output.

Logic Gates: AND

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 14

A = 0 , B = 0 🡪 both diodes are forward biased 🡪 both diodes conduct 🡪out is LOW 🡪 0.

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The simples gates are AND and OR. They can be built from switches or using the simplest form of electronic logic - diode logic.

Logic Gates: AND

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 15

A = 0 , B = 0 🡪 both diodes are forward biased 🡪 both diodes conduct 🡪out is LOW 🡪 0.

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A = 0 , B = 1 🡪 DB is reverse biased 🡪 does not conduct,

DA is forward biased 🡪 conducts 🡪out is LOW 🡪 0.

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The simples gates are AND and OR. They can be built from switches or using the simplest form of electronic logic - diode logic.

Logic Gates: AND

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 16

A = 0 , B = 0 🡪 both diodes are forward biased 🡪 both diodes conduct 🡪out is LOW 🡪 0.

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A = 0 , B = 1 🡪 DB is reverse biased 🡪 does not conduct,

DA is forward biased 🡪 conducts 🡪out is LOW 🡪 0.

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A = 1 , B = 0 🡪 DA is reverse biased 🡪 does not conduct,

DB is forward biased 🡪 conducts 🡪out is LOW 🡪 0.

​

The simples gates are AND and OR. They can be built from switches or using the simplest form of electronic logic - diode logic.

Logic Gates: AND

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 17

A = 0 , B = 0 🡪 both diodes are forward biased 🡪 both diodes conduct 🡪out is LOW 🡪 0.

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A = 0 , B = 1 🡪 DB is reverse biased 🡪 does not conduct,

DA is forward biased 🡪 conducts 🡪out is LOW 🡪 0.

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A = 1 , B = 0 🡪 DA is reverse biased 🡪 does not conduct,

DB is forward biased 🡪 conducts 🡪out is LOW 🡪 0.

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A = 1 , B = 1 🡪 both diodes are reverse biased 🡪

both the diodes do not conduct 🡪 out is HIGH 🡪 1.

The simples gates are AND and OR. They can be built from switches or using the simplest form of electronic logic - diode logic.

Logic Gates: OR

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 18

A = 0 , B = 0 🡪 both diodes are reverse biased 🡪 does not conduct 🡪out is LOW 🡪 0.

​

A = 0 , B = 1 🡪 DA is reverse biased 🡪 does not conduct,

DB is forward biased 🡪 conducts 🡪out is HIGH 🡪 1.

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A = 1 , B = 0 🡪 DB is reverse biased 🡪 does not conduct,

DA is forward biased 🡪 conducts 🡪out is HIGH 🡪 1.

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A = 1 , B = 1 🡪 both diodes are reverse biased 🡪

both the diodes conduct 🡪 out is HIGH 🡪 1.

Logic Gates: NAND & NOR

• The simple diode logic allows AND and OR, but not inverters 🡪 an incomplete form of logic.
• Also, without some kind of amplification it is not possible to have such basic logic operations cascaded as required for more complex logic functions.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 19

Logic Gates: NAND & NOR

• The simple diode logic allows AND and OR, but not inverters 🡪 an incomplete form of logic.
• Also, without some kind of amplification it is not possible to have such basic logic operations cascaded as required for more complex logic functions.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 20

• However, any gate can be built from NAND or NOR gates. This enables a circuit to be built from just one type of gate, either NAND or NOR.
• To build NAND or NOR inverter is required 🡪 transistors needed.

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Logic Gates: NAND & NOR

• The simple diode logic allows AND and OR, but not inverters 🡪 an incomplete form of logic.
• Also, without some kind of amplification it is not possible to have such basic logic operations cascaded as required for more complex logic functions.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 21

• However, any gate can be built from NAND or NOR gates. This enables a circuit to be built from just one type of gate, either NAND or NOR.
• To build NAND or NOR inverter is required 🡪 transistors needed.

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Conclusion.

• To build a functionally complete logic systems transistors are used.

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• The most basic digital building block is the inverter.

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Diode-Transistor Logic (DTL) Gate

• The inversion and level-restoration problem associated with diode logic can be solved by adding a diode and transistor to form the diode-transistor logic (DTL) gate
• It will be analyzed in detail sin Chapter 9; here is a brief overview.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 22

Diode-Transistor Logic (DTL) Gate

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 23

On the left, diodes D1 and D2 are both off, whereas D3 and Q1 are on. Node 1 is at 1.3 V:

V1 = VD3 + VBE = 0.6 V + 0.7 V = 1.3 V

The current I through resistor RB and diode D3 becomes the base current IB of transistor Q1. The

value of IB is designed to cause Q1 to saturate so that v_O = VCESAT (for example, 0.05 to 0.1 V).

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• The inversion and level-restoration problem associated with diode logic can be solved by adding a diode and transistor to form the diode-transistor logic (DTL) gate
• It will be analyzed in detail sin Chapter 9; here is a brief overview.

Diode-Transistor Logic (DTL) Gate

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 24

On the right, input B is now at 0 V, corresponding to a logical 0. Diode D2 is conducting,

holding node 1 at 0.6 V. Now diode D3 and transistor Q1 must both be off, because the voltage at

node 1 is now less than the two diode voltage drops required to turn on both D3 and Q1. The base

current of Q1 is now zero; Q1 will be off with IC = 0, and the output voltage will be at +3.3 V,

corresponding to a logical 1. A similar situation holds for the circuit if both inputs are low.

• The inversion and level-restoration problem associated with diode logic can be solved by adding a diode and transistor to form the diode-transistor logic (DTL) gate
• It will be analyzed in detail sin Chapter 9; here is a brief overview.

Diode-Transistor Logic (DTL) Gate

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 25

On the left, diodes D1 and D2 are both off, whereas D3 and Q1 are on. Node 1 is at 1.3 V:

V1 = VD3 + VBE = 0.6 V + 0.7 V = 1.3 V

The current I through resistor RB and diode D3 becomes the base current IB of transistor Q1. The

value of IB is designed to cause Q1 to saturate so that v_O = VCESAT (for example, 0.05 to 0.1 V).

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On the right, input B is now at 0 V, corresponding to a logical 0. Diode D2 is conducting,

holding node 1 at 0.6 V. Now diode D3 and transistor Q1 must both be off, because the voltage at

node 1 is now less than the two diode voltage drops required to turn on both D3 and Q1. The base

current of Q1 is now zero; Q1 will be off with IC = 0, and the output voltage will be at +3.3 V,

corresponding to a logical 1. A similar situation holds for the circuit if both inputs are low.

• The inversion and level-restoration problem associated with diode logic can be solved by adding a diode and transistor to form the diode-transistor logic (DTL) gate
• It will be analyzed in detail sin Chapter 9; here is a brief overview.

The Ideal Inverter

The ideal inverter has the following voltage transfer characteristic (VTC) and is described by the following symbol

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 26

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The Ideal Inverter

The ideal inverter has the following voltage transfer characteristic (VTC) and is described by the following symbol

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 27

V₊ and V_- are the supply rails

V_H and V_L describe the high and low logic levels at the output

Inverter - circuit

An inverter operating with power supplies at V₊ and 0 V can be implemented using a switch with a resistive load.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 28

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MOSFET

Inverter - circuit

An inverter operating with power supplies at V₊ and 0 V can be implemented using a switch with a resistive load.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 29

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Q-point

Inverter - circuit

An inverter operating with power supplies at V₊ and 0 V can be implemented using a switch with a resistive load.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 30

Q-point

Inverter - circuit

An inverter operating with power supplies at V₊ and 0 V can be implemented using a switch with a resistive load.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 31

VTC of Non-Ideal Inverter� Voltage Level Definitions

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 32

For the (VTC) of the non-ideal inverter no Vref is defined. There is now an undefined logic state. The points (V_IH ,V_OL ) and (V_IL ,V_OH ) are defined as the points on the VTC curve where slope is -1.

Logic Voltage Level Definitions

• V_L – The nominal voltage corresponding to a low-logic

state at the output of a logic gate for v_i = V_H

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 33

Logic Voltage Level Definitions

• V_L – The nominal voltage corresponding to a low-logic

state at the output of a logic gate for v_i = V_H

• V_H – The nominal voltage corresponding to a high-logic

state at the output of a logic gate for v_i = V_L

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 34

Logic Voltage Level Definitions

• V_L – The nominal voltage corresponding to a low-logic

state at the output of a logic gate for v_i = V_H

• V_H – The nominal voltage corresponding to a high-logic

state at the output of a logic gate for v_i = V_L

• V_IL – The maximum input voltage that will be recognized

as a low input logic level

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 35

Logic Voltage Level Definitions

• V_L – The nominal voltage corresponding to a low-logic

state at the output of a logic gate for v_i = V_H

• V_H – The nominal voltage corresponding to a high-logic

state at the output of a logic gate for v_i = V_L

• V_IL – The maximum input voltage that will be recognized

as a low input logic level

• V_IH – The minimum input voltage that will be recognized

as a high input logic level

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 36

Logic Voltage Level Definitions

• V_L – The nominal voltage corresponding to a low-logic

state at the output of a logic gate for v_i = V_H

• V_H – The nominal voltage corresponding to a high-logic

state at the output of a logic gate for v_i = V_L

• V_IL – The maximum input voltage that will be recognized

as a low input logic level

• V_IH – The minimum input voltage that will be recognized

as a high input logic level

• V_OH – The output voltage corresponding to an input

voltage of V_IL

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 37

Logic Voltage Level Definitions

• V_L – The nominal voltage corresponding to a low-logic

state at the output of a logic gate for v_i = V_H

• V_H – The nominal voltage corresponding to a high-logic

state at the output of a logic gate for v_i = V_L

• V_IL – The maximum input voltage that will be recognized

as a low input logic level

• V_IH – The minimum input voltage that will be recognized

as a high input logic level

• V_OH – The output voltage corresponding to an input

voltage of V_IL

• V_OL – The output voltage corresponding to an input

voltage of V_IH

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 38

Logic Voltage Level Definitions

• V_L – The nominal voltage corresponding to a low-logic

state at the output of a logic gate for v_i = V_H

• V_H – The nominal voltage corresponding to a high-logic

state at the output of a logic gate for v_i = V_L

• V_IL – The maximum input voltage that will be recognized

as a low input logic level

• V_IH – The minimum input voltage that will be recognized

as a high input logic level

• V_OH – The output voltage corresponding to an input

voltage of V_IL

• V_OL – The output voltage corresponding to an input

voltage of V_IH

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Typically, V_-=0.

V₊=5 for bipolar logic,

V₊=1.8, 2.5, 3.3 for MOS logic

V₊=1.0-1.5 for ultra low voltage logic

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 39

Noise Margins

• Noise margins represent “safety margins” that prevent the circuit from producing erroneous outputs in the presence of noisy inputs
• Noise margins are defined for low and high input levels using the following equations:

NM_L = V_IL – V_OL

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NM_H = V_OH – V_IH

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 40

Logic Gate Design Goals

• An ideal logic gate is highly nonlinear and attempts to quantize the input signal to two discrete states. In an actual gate, the designer should attempt to minimize the undefined input region while maximizing noise margins

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 41

Logic Gate Design Goals

• An ideal logic gate is highly nonlinear and attempts to quantize the input signal to two discrete states. In an actual gate, the designer should attempt to minimize the undefined input region while maximizing noise margins
• The logic gate is unidirectional. Changes at the output should have no effect on the input.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 42

Logic Gate Design Goals

• An ideal logic gate is highly nonlinear and attempts to quantize the input signal to two discrete states. In an actual gate, the designer should attempt to minimize the undefined input region while maximizing noise margins
• The logic gate is unidirectional. Changes at the output should have no effect on the input.
• Voltage levels at the output of one gate should be compatible with the input levels of a following gate

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 43

Logic Gate Design Goals

• An ideal logic gate is highly nonlinear and attempts to quantize the input signal to two discrete states. In an actual gate, the designer should attempt to minimize the undefined input region while maximizing noise margins
• The logic gate is unidirectional. Changes at the output should have no effect on the input.
• Voltage levels at the output of one gate should be compatible with the input levels of a following gate
• The output of one gate should be capable of driving the input of more than one gate: the gate should have sufficient fan-out and fan-in capabilities

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 44

Logic Gate Design Goals

• An ideal logic gate is highly nonlinear and attempts to quantize the input signal to two discrete states. In an actual gate, the designer should attempt to minimize the undefined input region while maximizing noise margins
• The logic gate is unidirectional. Changes at the output should have no effect on the input.
• Voltage levels at the output of one gate should be compatible with the input levels of a following gate
• The output of one gate should be capable of driving the input of more than one gate: the gate should have sufficient fan-out and fan-in capabilities
• The gate should consume minimal power (and area for ICs) and still operate under the design specifications

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 45

Dynamic Response of Logic Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 46

• An important characteristic of the logical gates is the response in the time domain
• To describe the typical pulse signal at the input, we introduce:

The rise and fall times: t_f and t_r, are measured at the 10% and 90% points on the transitions between the two states as shown by the following expressions:

V_10% = V_L + 0.1ΔV

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V_90% = V_L + 0.9ΔV = V_H – 0.1ΔV

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where ΔV is the logic swing given by ΔV = V_H - V_L

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Dynamic Response of Logic Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 47

• For the input on the top, will the output will be like the signal on the bottom plot?

Dynamic Response of Logic Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 48

• For the input on the top, will the output will be like the signal on the bottom plot?
• No, It will be delayed.

Dynamic Response of Logic Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 49

• For the input on the top, will the output will be like the signal on the bottom plot?
• No, It will be delayed.
• Propagation delay describes the amount of time between the input reaching the 50% point and the output reaching the 50% point. The 50% point is described by the following:

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• The high-to-low propagation delay, τ_PHL, and the low-to-high propagation delay, τ_PLH, are usually not equal, but can be combined as an average value:

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NMOS Logic Design

• MOS transistors (both PMOS and NMOS) can be combined with resistive loads to create single channel logic gates.

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 50

NMOS Logic Design

• MOS transistors (both PMOS and NMOS) can be combined with resistive loads to create single channel logic gates.

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• In most logic design situations, the power supply voltage is predetermined by either technology reliability constraints or system-level criteria
• The circuit designer is limited to altering circuit topology and the width-to-length (W/L) ratio since the other factors are dependent upon processing parameters

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 51

NMOS Logic Design

• MOS transistors (both PMOS and NMOS) can be combined with resistive loads to create single channel logic gates.

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• In most logic design situations, the power supply voltage is predetermined by either technology reliability constraints or system-level criteria
• The circuit designer is limited to altering circuit topology and the width-to-length (W/L) ratio since the other factors are dependent upon processing parameters

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• We begin our study of MOS logic circuit design by considering the detailed design of the NMOS inverter with the resistor load.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 52

NMOS Logic Design

• MOS transistors (both PMOS and NMOS) can be combined with resistive loads to create single channel logic gates.

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• In most logic design situations, the power supply voltage is predetermined by either technology reliability constraints or system-level criteria
• The circuit designer is limited to altering circuit topology and the width-to-length (W/L) ratio since the other factors are dependent upon processing parameters

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• We begin our study of MOS logic circuit design by considering the detailed design of the NMOS inverter with the resistor load.
• In integrated logic circuits, the load resistor occupies too much silicon area, and is replaced by a second NMOS transistor. This “load device” can be connected in three different configurations called the saturated load, linear load, and depletion-mode load circuits.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 53

NMOS Inverter with a Resistive Load

• The basic inverter circuit consists of an NMOS switching device M_S and a resistor load element.

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• M_S is the switching transistor used to “pull” the output high - toward to the power supply V_DD

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• The resistor R is used to “pull” the output low, to force v_O to V_L

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• The size of R and the W/L ratio of M_S are the design factors that need to be chosen.

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 54

NMOS Inverter with a Resistive Load

When the input voltage is at a low state, v_I = V_L , M_S should be cut off, with i_D = 0, so that

v_O = V_DD = V_H

Thus, in this particular logic circuit, the value of V_H is set by the power supply voltage V_DD = 2.5V.

To ensure that switching transistor M_S is cut off when the input is in the low logic state, V_L is designed to be 25 to 50 percent of the threshold voltage V_TN of switch M_S. This choice also provides a reasonable value for noise margin NML .

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 55

The equation for the output voltage (load line): v_O = v_DS = V_DD − i_D R

NMOS Inverter with a Resistive Load

When the input voltage is at a low state, v_I = V_L , M_S should be cut off, with i_D = 0, so that

v_O = V_DD = V_H

Thus, in this particular logic circuit, the value of V_H is set by the power supply voltage V_DD = 2.5V.

To ensure that switching transistor M_S is cut off when the input is in the low logic state, V_L is designed to be 25 to 50 percent of the threshold voltage V_TN of switch M_S. This choice also provides a reasonable value for noise margin NML .

​

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 56

When the input voltage is at a high state, v_I = V_H , switch M_S is set in the triode region by the design of W/L parameter and load line to ensure that v_O = V_L.

The equation for the output voltage (load line): v_O = v_DS = V_DD − i_D R

NMOS with Resistive Load�Design Example (1)

• Design a NMOS resistive load inverter for
• V_DD = 3.3 V
• P = 0.1 mW when V_L = 0.2 V
• K_n = 60 μA/V²
• V_TN = 0.75 V

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 57

• Find the value of the load resistor R and the W/L ratio of the switching transistor M_S

NMOS with Resistive Load�Design Example (2)

• First the value of the current through the resistor (for v_O = V_L) must be determined by using the following:

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• The value of the resistor can now be found by the following, which assumes that the transistor is on and the output is low:

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 58

NMOS with Resistive Load�Design Example (3)

• For v_I = V_H = 3.3 V, and v_O = V_L = 0.2V, the transistor’s drain-source voltage �V_DS =V_L will be less than V_GS -V_TN=V_H -V_TN

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• Therefore it will be operating in the triode region. Using the triode region equation for the MOSFET, the W/L ratio can be found:

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 59

On-Resistance of the Switching Device

• The NMOS resistive load inverter can be thought of as a resistive voltage divider when the output is low:

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where the On-Resistance R_on of the NMOS can be calculated with the following expression:

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• Note : �1. R_on should be kept small compared to R to ensure that V_L remains low. �2. Its value is nonlinear, since it has a dependence on v_DS.

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 60

Noise Margin Analysis

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 61

The following equations (base on the calculation of the derivatives of v_O =V_DD –i_DR with respect to v_I ) can be used to determine the various parameters needed to determine the noise margin of NMOS resistive load inverters

Load Resistor Issue

• For completely integrated circuits, R must be implemented on chip using the shown structure.

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 62

Load Resistor Issue

• For completely integrated circuits, R must be implemented on chip using the shown structure.

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• If the resistor width W were made a line width of 1μm (minimum feature size F), then the length L would be 2880 μm, and the area would be 2880 μm².

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 63

Load Resistor Issue

• For completely integrated circuits, R must be implemented on chip using the shown structure.

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• If the resistor width W were made a line width of 1μm (minimum feature size F), then the length L would be 2880 μm, and the area would be 2880 μm².

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• For the transistor M_S, W/L was found to be 2.22/1. If the device channel length is equal to the minimum feature size of 1 μm, then the gate area of the NMOS is only 2.22 μm². Thus, the load resistor would consume more than 1000 times the area of the switching transistor M_S.

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 64

Load Resistor Issue

• For completely integrated circuits, R must be implemented on chip using the shown structure.

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• If the resistor width W were made a line width of 1μm (minimum feature size F), then the length L would be 2880 μm, and the area would be 2880 μm².

​

• For the transistor M_S, W/L was found to be 2.22/1. If the device channel length is equal to the minimum feature size of 1 μm, then the gate area of the NMOS is only 2.22 μm². Thus, the load resistor would consume more than 1000 times the area of the switching transistor M_S.

​

• This is simply not an acceptable utilization of area in IC design.

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 65

Load Resistor Issue

• For completely integrated circuits, R must be implemented on chip using the shown structure.

​

• If the resistor width W were made a line width of 1μm (minimum feature size F), then the length L would be 2880 μm, and the area would be 2880 μm².

​

• For the transistor M_S, W/L was found to be 2.22/1. If the device channel length is equal to the minimum feature size of 1 μm, then the gate area of the NMOS is only 2.22 μm². Thus, the load resistor would consume more than 1000 times the area of the switching transistor M_S.

​

• This is simply not an acceptable utilization of area in IC design.

​

• The solution to this problem is to replace the load resistor with a transistor.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 66

Using Transistors in Place of a Resistor

NMOS load transistor with

a) gate connected to the source

b) gate connected to ground

c) gate connected to V_DD

d) gate biased to linear region

e) a depletion-mode NMOSFET

f) gate grounded PMOS load

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 67

We are replacing a 2-terminal device with a 3(4)-terminal device and need to figure our what to do with the gate (since drain and source are conducting).

Using Transistors in Place of a Resistor

NMOS load with

a) gate connected to the source

b) gate connected to ground

c) gate connected to V_DD

d) gate biased to linear region

e) a depletion-mode NMOSFET

f) gate grounded PMOS load

​

Note that a) and b) are not useful, since with 0 at the gate, the enhancement mode NMOS is not conducting.

​

We’ll consider other methods starting from (c)

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 68

We are replacing a 2-terminal device with a 3(4)-terminal device and need to figure our what to do with the gate (since drain and source are conducting).

NMOS Saturated Load Inverter

Schematic for a NMOS

saturated load inverter

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 69

The substrate is common and grounded:

It’s the (c) on diagram, called saturated because M_L is in saturation region:

v_DS = v_GS 🡪 v_DS ≥ v_GS − V_TN for V_TN ≥ 0

NMOS Saturated Load Inverter

Schematic for a NMOS

saturated load inverter

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 70

The substrate is common and grounded:

🡪 v_SB=0 for M_S .

It’s the (c) on diagram, called saturated because M_L is in saturation region:

v_DS = v_GS 🡪 v_DS ≥ v_GS − V_TN for V_TN ≥ 0

NMOS Saturated Load Inverter

Schematic for a NMOS

saturated load inverter

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 71

The substrate is common and grounded:

🡪 v_SB=0 for M_S .

🡪 v_SB=v_O for M_L ,

It’s the (c) on diagram, called saturated because M_L is in saturation region:

v_DS = v_GS 🡪 v_DS ≥ v_GS − V_TN for V_TN ≥ 0

NMOS Saturated Load Inverter

Schematic for a NMOS

saturated load inverter

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 72

The substrate is common and grounded:

🡪 v_SB=0 for M_S .

🡪 v_SB=v_O for M_L ,

thus V_TN is generally different for both.

It’s the (c) on diagram, called saturated because M_L is in saturation region:

v_DS = v_GS 🡪 v_DS ≥ v_GS − V_TN for V_TN ≥ 0

NMOS Saturated Load Inverter-Design Strategy

• Given V_DD, V_L, and the power level, find I_DD from V_DD and power.

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 73

NMOS Saturated Load Inverter-Design Strategy

• Given V_DD, V_L, and the power level, find I_DD from V_DD and power.

​

• Assume M_S off, and find high output voltage level V_H

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 74

NMOS Saturated Load Inverter-Design Strategy

• Given V_DD, V_L, and the power level, find I_DD from V_DD and power.

​

• Assume M_S off, and find high output voltage level V_H

​

• Use the value of V_H for the gate voltage of M_S and calculate (W/L)_S of the switching transistor based on the design values of I_DD and V_L

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 75

NMOS Saturated Load Inverter-Design Strategy

• Given V_DD, V_L, and the power level, find I_DD from V_DD and power.

​

• Assume M_S off, and find high output voltage level V_H

​

• Use the value of V_H for the gate voltage of M_S and calculate (W/L)_S of the switching transistor based on the design values of I_DD and V_L

​

• Use the value of V_H for the gate voltage of M_S and find (W/L)_L of the load transistor based on I_DD and V_L

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 76

NMOS Saturated Load Inverter-Design Strategy

• Given V_DD, V_L, and the power level, find I_DD from V_DD and power.

​

• Assume M_S off, and find high output voltage level V_H

​

• Use the value of V_H for the gate voltage of M_S and calculate (W/L)_S of the switching transistor based on the design values of I_DD and V_L

​

• Use the value of V_H for the gate voltage of M_S and find (W/L)_L of the load transistor based on I_DD and V_L

​

• Check the operating region assumptions of M_S and M_L for v_o = V_L

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 77

NMOS Saturated Load Inverter - Example

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 78

Design an saturated load inverter given the following specifications:

​

​

NMOS Saturated Load Inverter - Example

• First, set v_i = V_H ,v_O = V_L, M_S - on, and find the value of the current through the resistor using the power :

​

​

​

​

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 79

Design an saturated load inverter given the following specifications:

​

​

LIN

SAT

NMOS Saturated Load Inverter - Example

• First, set v_i = V_H ,v_O = V_L, M_S - on, and find the value of the current through the resistor using the power :

​

​

​

• Now set v_i = V_L ,v_O = V_H, M_S - off, M_L - off and then, find V_H (since now, V_H is not equal V_DD.) Why?

​

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 80

Design an saturated load inverter given the following specifications:

​

​

NMOS Saturated Load Inverter - Example

• First, set v_i = V_H ,v_O = V_L, M_S - on, and find the value of the current through the resistor using the power :

​

​

​

• Now set v_i = V_L ,v_O = V_H, M_S - off, M_L - off and then, find V_H (since now, V_H is not equal V_DD.) Why?
• When M_S turns off from the on state, the current I_DD will stop when the value of v_GSL will reach V_TNL, (v_GS > V_TN, for I_DD to exist)

v_GSL = V_DD − v_O = V_TN 🡪 V_H = V_DD − V_TN .

Thus, taking into account the body effect (γ) and surface potential parameter (φ_F):

​

​

​

​

(The output cannot exceed the positive power supply voltage.)

​

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 81

Design an saturated load inverter given the following specifications:

​

​

NMOS Saturated Load Inverter - Example

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 82

• Now we can find W/L for both transistors M_S and then M_L.
• Set v_i = V_H , v_o = V_L: �M_S is in the triode region (on) �M_L is in saturation (on).

Check the operating region. For the switch, V_GS − V_TN = 2.11 − 0.75 = 1.36 V, which is greater than �V_DS = 0.2 V, and the triode region assumption is correct. For the load device, V_GS − V_TN =3.1 − 0.81 = 2.29 V and is less than V_DS = 3.1 V, which is consistent with the saturation region of operation.

LIN

SAT

NMOS Saturated Load Inverter -Noise Margin

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 83

From the PSPICE simulation typical noise margins are:

NM_H = V_OH - V_IH = 1.55 - 1.42 = 0.33 V

NM_L = V_IL - V_OL = 0.90 - 0.38 = 0.22 V

The detailed analysis of the noise margins for saturated load inverter is quite tedious. Instead, the PSPICE simulation can be used. Example:

NMOS Inverter with a Linear Load

• This inverter has a load transistor that is biased with V_GG defined by the following:

​

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 84

NMOS Inverter with a Linear Load

• This inverter has a load transistor that is biased with V_GG defined by the following:

​

​

• This causes the load transistor to operate in the linear region:

v_GSL − V_TNL = V_GG − v_o − V_TNL

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 85

NMOS Inverter with a Linear Load

• This inverter has a load transistor that is biased with V_GG defined by the following:

​

​

• This causes the load transistor to operate in the linear region:

v_GSL − V_TNL = V_GG − v_o − V_TNL

≥ V_DD + V_TNL − v_o − V_TNL

≥ V_DD − v_o = v_DSL

​

• For this value of V_GG, the output voltage in the high output state V_H is equal to V_DD:

M_S -off, i_D=0 🡪 v_DSL=0 (linear region) 🡪

v_DSL= V_DD − v_o = V_DD − V_H =0 🡪 V_H = V_DD

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 86

NMOS Inverter with a Linear Load

• This inverter has a load transistor that is biased with V_GG defined by the following:

​

​

• This causes the load transistor to operate in the linear region:

v_GSL − V_TNL = V_GG − v_o − V_TNL

≥ V_DD + V_TNL − v_o − V_TNL

≥ V_DD − v_o = v_DSL

​

• For this value of V_GG, the output voltage in the high output state V_H is equal to V_DD:

M_S -off, i_D=0 🡪 v_DSL=0 (linear region) 🡪

v_DSL= V_DD − v_o = V_DD − V_H =0 🡪 V_H = V_DD

​

• The W/L ratios for M_S and M_L can be calculated as in previous section ( easier, since V_H is equal to V_DD)

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 87

NMOS Inverter with a Depletion-mode Load

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 88

• The saturated load and linear load circuits were used when all the devices had the same threshold voltages in early NMOS and PMOS technologies.
• However, once ion-implantation technology was perfected, it became possible to selectively adjust the threshold of the load transistors to alter their characteristics to become those of NMOS depletion mode devices with V_TN < 0.

D

E

NMOS Inverter with a Depletion-mode Load

• When M_S is off (v_I = V_L ), the current� i_D =0, hence from the linear region (which is now possible even for v_GSL =0 because of depletion mode) we have v_DSL =0 (< v_GSL - V_TN >0) and output voltage rises to V_H = V_DD

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 89

• The saturated load and linear load circuits were used when all the devices had the same threshold voltages in early NMOS and PMOS technologies.
• However, once ion-implantation technology was perfected, it became possible to selectively adjust the threshold of the load transistors to alter their characteristics to become those of NMOS depletion mode devices with V_TN < 0.

D

E

LIN

i_D =0

NMOS Inverter with a Depletion-mode Load

• When M_S is off (v_I = V_L ), the current� i_D =0, hence from the linear region (which is now possible even for v_GSL =0 because of depletion mode) we have v_DSL =0 (< v_GSL - V_TN >0) and output voltage rises to V_H = V_DD

​

• For M_S on and conducting (v_I = V_H ), �v_O = V_L, M_L is designed to be saturated (v_DSL = 2.5 - v_O > v_GSL - V_TN ) and M_S , as usual, in the triode region.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 90

• The saturated load and linear load circuits were used when all the devices had the same threshold voltages in early NMOS and PMOS technologies.
• However, once ion-implantation technology was perfected, it became possible to selectively adjust the threshold of the load transistors to alter their characteristics to become those of NMOS depletion mode devices with V_TN < 0.

D

E

LIN

SAT

• Then we set input to V_H a(both transistors on) and find W/L

​

• To find (W/L)_L given i_DL (which we find from power requirements) we use the saturation mode for M_L with v_GS =0 :

​

​

​

• To find (W/L)_S where V_H = V_DD, use the same technique as used for the resistor load inverter:

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 91

NMOS Inverter with a Depletion-mode Load

NMOS Inverter with a Depletion-mode Load - Noise Margins

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 92

From PSPICE simulation, typical noise margins are:

NM_H = V_OH - V_IH = 2.35 - 1.45 = 0.90 V

NM_L = V_IL - V_OL = 0.93 - 0.50 = 0.43 V

The detailed analysis of the noise margins for saturated load inverter is quite tedious. Instead, the PSPICE simulation can be used. Example:

Pseudo NMOS Inverter

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 93

• It is possible to replace the load resistor with a PMOS transistor with its source connected to V_DD, its drain connected to the output node and its gate grounded.
• This circuit is called pseudo NMOS since circuit operates very similar to NMOS although has a PMOS in it.

​

LIN

SAT

• For v_o = V_L (M_S is on), M_L is in the saturation region.

​

​

Pseudo NMOS Inverter

• For v_o = V_L (M_S is on), M_L is in the saturation region.

​

• For v_o = V_H (M_S is off) M_L is in the triode region (i=0, �0=V_DS < |V_GS - V_TN |=|2.5 - V_TN |.

​

• For this circuit, V_H = V_DD because M_L is in the linear triode region and V_DS =0 when M_S is off.

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 94

• It is possible to replace the load resistor with a PMOS transistor with its source connected to V_DD, its drain connected to the output node and its gate grounded.
• This circuit is called pseudo NMOS since circuit operates very similar to NMOS although has a PMOS in it.

​

LIN

Pseudo NMOS Inverter

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 95

• It is possible to replace the load resistor with a PMOS transistor with its source connected to V_DD, its drain connected to the output node and its gate grounded.
• This circuit is called pseudo NMOS since circuit operates very similar to NMOS although has a PMOS in it.

​

LIN

• For v_o = V_L (M_S is on), M_L is in the saturation region.

​

• For v_o = V_H (M_S is off) M_L is in the triode region (i=0, �0=V_DS < |V_GS - V_TN |=|2.5 - V_TN |.

​

• For this circuit, V_H = V_DD because M_L is in the linear triode region and V_DS =0 when M_S is off.

​

Pseudo NMOS Inverter Design - Example

• Design an pseudo NMOS inverter given the following specifications:

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 96

Pseudo NMOS Inverter Design - Example

• Design an pseudo NMOS inverter given the following specifications:

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 97

• First calculate (W/L)_P to limit inverter current to 80 uA.

​

Pseudo NMOS Inverter Design - Example

• Design an pseudo NMOS inverter given the following specifications:

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 98

• First calculate (W/L)_P to limit inverter current to 80 uA.

​

M_S is on, M_L is in saturation:

LIN

SAT

Pseudo NMOS Inverter Design - Example

• Now calculate (W/L)_S for the same condition and current of 80 uA.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 99

LIN

SAT

Pseudo NMOS Inverter - Noise Margins

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 100

From SPICE simulation, typical noise margins are:

NM_H = V_OH - V_IH = 2.33 - 1.58 = 0.75 V

NM_L = V_IL - V_OL = 0.95 - 0.49 = 0.46 V

NMOS Inverter Summary

• Resistive load inverter takes up too much area for and IC design.

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 101

NMOS Inverter Summary

• Resistive load inverter takes up too much area for and IC design.

​

• The saturated load configuration is the simplest design, but V_H never reaches V_DD, and it has a slow switching speed.

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 102

NMOS Inverter Summary

• Resistive load inverter takes up too much area for and IC design.

​

• The saturated load configuration is the simplest design, but V_H never reaches V_DD, and it has a slow switching speed.

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• The linear load inverter fixes the speed and logic level issues, but it requires an additional power supply for the load gate.

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 103

NMOS Inverter Summary

• Resistive load inverter takes up too much area for and IC design.

​

• The saturated load configuration is the simplest design, but V_H never reaches V_DD, and it has a slow switching speed.

​

• The linear load inverter fixes the speed and logic level issues, but it requires an additional power supply for the load gate.

​

• The depletion-mode NMOS load requires the most processing steps, but needs small area to achieve the high speed, V_H = V_DD, and best combination of noise margins.

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​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 104

NMOS Inverter Summary

• Resistive load inverter takes up too much area for and IC design.

​

• The saturated load configuration is the simplest design, but V_H never reaches V_DD, and it has a slow switching speed.

​

• The linear load inverter fixes the speed and logic level issues, but it requires an additional power supply for the load gate.

​

• The depletion-mode NMOS load requires the most processing steps, but needs small area to achieve the high speed, V_H = V_DD, and best combination of noise margins.

​

• The Pseudo NMOS inverter offers the best speed with the lowest area.

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 105

Typical Inverter Characteristics

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 106

Reference of NMOS Inverter Designs

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 107

NOR Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 108

• To obtain the complete logical family we need inverter and AND or OR function, or just one NAND or NOR element.

​

​

NOR Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 109

• To obtain the complete logical family we need inverter and AND or OR function, or just one NAND or NOR element.
• This type of element can be easily created by replacing one switch with two switches in parallel for NOR or in series for NAND.

​

​

NOR Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 110

• To obtain the complete logical family we need inverter and AND or OR function, or just one NAND or NOR element.
• This type of element can be easily created by replacing one switch with two switches in parallel for NOR or in series for NAND.

​

​

NOR Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 111

• To obtain the complete logical family we need inverter and AND or OR function, or just one NAND or NOR element.
• This type of element can be easily created by replacing one switch with two switches in parallel for NOR or in series for NAND.

​

​

NOR Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 112

• To obtain the complete logical family we need inverter and AND or OR function, or just one NAND or NOR element.
• This type of element can be easily created by replacing one switch with two switches in parallel for NOR or in series for NAND.

​

​

NOR Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 113

• To obtain the complete logical family we need inverter and AND or OR function, or just one NAND or NOR element.
• This type of element can be easily created by replacing one switch with two switches in parallel for NOR or in series for NAND.

​

​

NOR Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 114

• To obtain the complete logical family we need inverter and AND or OR function, or just one NAND or NOR element.
• This type of element can be easily created by replacing one switch with two switches in parallel for NOR or in series for NAND.

​

​

NOR Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 115

• To obtain the complete logical family we need inverter and AND or OR function, or just one NAND or NOR element.
• This type of element can be easily created by replacing one switch with two switches in parallel for NOR or in series for NAND.

​

​

• The worst condition for the output low (to have it as low as possible) is when only one switch is closed (since R_on for both are in parallel).

​

​

NOR Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 116

• To obtain the complete logical family we need inverter and AND or OR function, or just one NAND or NOR element.
• This type of element can be easily created by replacing one switch with two switches in parallel for NOR or in series for NAND.

​

​

• The worst condition for the output low (to have it as low as possible) is when only one switch is closed (since R_on for both are in parallel).
• Thus the M/L ratio should be chosen the same as for one switch.

​

​

NOR Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 117

• To obtain the complete logical family we need inverter and AND or OR function, or just one NAND or NOR element.
• This type of element can be easily created by replacing one switch with two switches in parallel for NOR or in series for NAND.

​

​

• The worst condition for the output low (to have it as low as possible) is when only one switch is closed (since R_on for both are in parallel).
• Thus the M/L ratio should be chosen the same as for one switch.
• When both are closed, the V_L at the output will be even lower then for one.

​

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NAND Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 118

NAND Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 119

NAND Gates

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 120

NAND Gate Device Size Selection

• Consider the equivalent of switching transistors in the ‘on” state as R_on.

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 121

NAND Gate Device Size Selection

• Consider the equivalent of switching transistors in the ‘on” state as R_on.
• To keep the low voltage level comparable with simple inverter, the desired R_on of M_A and M_B must be 0.5R_on of M_S switch.

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​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 122

NAND Gate Device Size Selection

• Consider the equivalent of switching transistors in the ‘on” state as R_on.
• To keep the low voltage level comparable with simple inverter, the desired R_on of M_A and M_B must be 0.5R_on of M_S switch.
• This can be accomplished by approximately doubling (W/L)_A and (W/L)_B

​

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 123

NAND Gate Device Size Selection

• Consider the equivalent of switching transistors in the ‘on” state as R_on.
• To keep the low voltage level comparable with simple inverter, the desired R_on of M_A and M_B must be 0.5R_on of M_S switch.
• This can be accomplished by approximately doubling (W/L)_A and (W/L)_B

​

​

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 124

NAND Gate Device Size Selection (cont)

• Two sources of error that arise are that 1) V_SB’s and 2) V_GS’s of the two transistors are not equal 🡪 the values of V_TN should be adjusted (see problem 6.28)

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• The technique used to calculate the size of the load transistor for the NAND gate is exactly the same as for the depletion-load inverter.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 125

• An advantage of NMOS technology is that it is simple to design complex logic functions based on the NOR and NAND gates.

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​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 126

Complex NMOS Logic Design

• An advantage of NMOS technology is that it is simple to design complex logic functions based on the NOR and NAND gates.

​

• The typical problem that arises is the transistor sizing.

​

​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 127

Complex NMOS Logic Design

• An advantage of NMOS technology is that it is simple to design complex logic functions based on the NOR and NAND gates.

​

• The typical problem that arises is the transistor sizing.

​

• There are two ways to find the W/L ratios of the switching transistors
1. Use the worst-case path (most devices in series) and choose the W/L ratios to achieve the value of R_on equivalent to that of the inverter

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 128

Complex NMOS Logic Design

• An advantage of NMOS technology is that it is simple to design complex logic functions based on the NOR and NAND gates.

​

• The typical problem that arises is the transistor sizing.

​

• There are two ways to find the W/L ratios of the switching transistors
1. Use the worst-case path (most devices in series) and choose the W/L ratios to achieve the value of R_on equivalent to that of the inverter
2. Partitioning the circuit into a series sub-networks, and make the equivalent on-resistances equal

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 129

Complex NMOS Logic Design

Complex NMOS Logic Design (1)

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 130

Example 1. Design a logic function:

Y = A + B(C + D)

Base inverter:

Complex NMOS Logic Design (1)

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 131

Example 1. Design a logic function:

Y = A + B(C + D)

Base inverter:

Complex NMOS Logic Design (1)

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 132

Example 1. Design logic function:

Y = A + B(C + D)

Base inverter:

Complex NMOS Logic Design (1)

• Referring to the base inverter design, we have for the M_S W/L=2.22/1 in order to maintain the low output of 0.20V

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 133

Example 1. Design logic function:

Y = A + B(C + D)

Base inverter:

Complex NMOS Logic Design (1)

• Referring to the base inverter design, we have for the M_S W/L=2.22/1 in order to maintain the low output of 0.20V
• We’ll have the same for M_A (in parallel).

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​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 134

Example 1. Design logic function:

Y = A + B(C + D)

Base inverter:

Complex NMOS Logic Design (1)

• Referring to the base inverter design, we have for the M_S W/L=2.22/1 in order to maintain the low output of 0.20V
• We’ll have the same for M_A (in parallel).
• In another parallel branch we have a series connection, so M_B and combination of M_C and M_D should have double width W/L=4.44/1

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​

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 135

Example 1. Design logic function:

Y = A + B(C + D)

Base inverter:

Complex NMOS Logic Design (1)

• Referring to the base inverter design, we have for the M_S W/L=2.22/1 in order to maintain the low output of 0.20V
• We’ll have the same for M_A (in parallel).
• In another parallel branch we have a series connection, so M_B and combination of M_C and M_D should have double width W/L=4.44/1
• Finally, M_C and M_D are in parallel, so their W/L does not change.

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NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 136

Example 1. Design logic function:

Y = A + B(C + D)

Base inverter:

Complex NMOS Logic Design (2)

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 137

Example 2. Design logic function:

Y = A B + CDB = (A+CD)B

Base inverter :

Complex NMOS Logic Design (2)

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 138

Example 2. Design logic function:

Y = A B + CDB = (A+CD)B

Base inverter :

• The figure on the left shows the worst case method. The longest path is 3 transistors in series, so (W/L)=6.66 /1 is the size for each element in series.

Complex NMOS Logic Design (2)

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 139

Example 2. Design logic function:

Y = A B + CDB = (A+CD)B

Base inverter :

• The figure on the left shows the worst case method. The longest path is 3 transistors in series, so (W/L)=6.66 /1 is the size for each element in series. One M_A is in parallel with two transistors, so its W/L is halved.

Complex NMOS Logic Design (2)

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 140

Example 2. Design logic function:

Y = A B + CDB = (A+CD)B

Base inverter :

• The figure on the left shows the worst case method. The longest path is 3 transistors in series, so (W/L)=6.66 /1 is the size for each element in series. One M_A is in parallel with two transistors, so its W/L is halved.
• The figure on the right shows the partitioning technique : the longest path is 2, so (W/L)= 4.44/1.

Complex NMOS Logic Design (2)

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 141

Example 2. Design logic function:

Y = A B + CDB = (A+CD)B

Base inverter :

• The figure on the left shows the worst case method. The longest path is 3 transistors in series, so (W/L)=6.66 /1 is the size for each element in series. One M_A is in parallel with two transistors, so its W/L is halved.
• The figure on the right shows the partitioning technique : the longest path is 2, so (W/L)= 4.44/1. However, now we put 2 series transistors M_C and M_D in parallel with M_A , so their with is doubled.

Static Power Dissipation

• Static Power Dissipation is the average power dissipation of the logic gate for the high and low logic states. If the duty cycle is 50% it is:

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• I_DDH = current in the circuit for v_O = V_H
• I_DDL = current in the circuit for v_O = V_L

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• Since I_DDH = 0 for v_O = V_H :

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• If the duty cycle is different, 2 in the denominator should be changed appropriatly.

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 142

Dynamic Power Dissipation

• Dynamic Power Dissipation is the power dissipated during the process of charging and discharging the load capacitance connected to the logic gate

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 143

Discharging

Charging

?

?

Dynamic Power Dissipation

• Dynamic Power Dissipation is the power dissipated during the process of charging and discharging the load capacitance connected to the logic gate

NJIT ECE271 Dr.Serhiy Levkov

Topic 7 - 144

Discharging

Charging

R_L