��Chapter-4�Central Processing Unit: � �

• Introduction,
• General Register Organization,
• Stack Organization,
• Instruction format,
• Addressing Modes Data transfer and manipulation,
• Program Control,
• Reduced Instruction Set Computer (RISC).

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Introduction

• The part of the computer that performs the bull of data-processing operations is called the central processing unit and is referred to as the CPU. The CPU is made up of three major parts, as shown in Fig.

General Register Organization

• In the programming examples of Chap. , we have shown that memory locations are needed for storing pointers, counters, return addresses, temporary results, and partial products during multiplication.
• Having to refer to memory locations for such applications is time consuming because memory access is the most time-consuming operation in a computer.

Register set with common ALU

• The output of each register is connected to two multiplexers (MUX) to form the two buses A and B . The selection lines in each multiplexer select one register or the input data for the particular bus.
• The A and B buses form the inputs to a common arithmetic logic unit (ALU).
• The operation selected in the ALU determines the arithmetic or logic micro operation that is to be performed.
• The result of the micro operation is available for output data and also goes into the inputs of all the registers. The register that receives the information from the output bus is selected by a decoder.
• The decoder activates one of the register load inputs, thus providing a transfer path between the data in the output bus and the inputs of the selected destination register.

• The control unit that operates the CPU bus system directs the information flow through the registers and ALU by selecting the various components in the system.

R 1 <--R2 + R3

1. MUX A selector (SELA): to place the content of R2 into bus A .

2 . MUX B selector (SELB): to place the content o f R 3 into bus B .

3 . ALU operation selector (OPR): to provide the arithmetic addition A + B .

4. Decoder destination selector (SELD): t o transfer the content o f the output bus into R 1 .

Control Word

• There are 14 binary selection inputs in the unit, and their combined value specifies a control word. The 14-bit control word is defined in Fig. It consists of four fields.
• Three fields contain three bits each, and one field has five bits. The three bits of SELA select a source register for the A input of the ALU.
• The three bits of SELB select a register for the B input of the ALU.
• The three bits of SELD select a destination register using the decoder and its seven load outputs. The five bits of OPR select one of the operations in the ALU.
• The 14-bit control word when applied to the selection inputs specify a particular micro operation.

Stack Organization

• A useful feature that is included in the CPU of most computers is a stack or last-in, first-out (UFO) list.
• A stack is a storage device that stores information in such a manner that the item stored last is the first item retrieved.
• The operation of a stack can be compared to a stack of trays. The last tray placed on top of the stack is the first to be taken off.

• Stack Pointer :

The register that holds the address for the stack is called a stack pointer (SP) because its value always points at the top item in the stack.

• The two operations of a stack are the insertion and deletion of items.
• The operation of insertion is called push (or push-down) because it can be thought of as the result of pushing a new item on top.
• The operation of deletion is called pop (or pop-up) because it can be thought of as the result of removing one item so that the stack pops up.

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Register Stack

• stack can be placed in a portion of a large memory or it can be organized as a collection of a finite number of memory words or registers.

• In a 64-word stack, the stack pointer contains 6 bits because 26 = 64. Since SP has only six bits, it cannot exceed a number greater than 63 (111111 in binary).
• When 63 is incremented by 1, the result is 0 since 111111 + 1 = 1000000 in binary, but SP can accommodate only the six least significant bits.
• Similarly, when 000000 is decremented by 1, the result is 1 1 1 1 1 1 . The one-bit register FULL is set to 1 when the stack is full, and the one-bit register EMTY is set to 1 when the stack is empty of items. DR is the data register that holds the binary data to be written into or read out of the stack.

Push operation

• SP <- SP + 1 Increment stack pointer
• M [SP] <- DR Write item on top of the stack
• If (SP = 0) then (FULL <--1) Check if stack is full
• EMTY <--0 Mark the stack not empty

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Pop operation

• DR <--M [SP] Read item from the top of stack

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• SP <--SP – 1 Decrement stack pointer

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• If (SP = 0) then (EMTY <--1) Check if stack is empty

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• FULL <--0 Mark the stack not full

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Reverse Polish Notation

• A stack organization is very effective for evaluating arithmetic expressions.
• The common mathematical method of writing arithmetic expressions imposes difficulties when evaluated by a computer.
• The common arithmetic expressions are written in infix notation, with each operator written between the operands. Consider the simple arithmetic expression

A • B + C • D

• The postfix notation, referred to as reverse Polish notation (RPN), places the operator after the operands.
• The following examples demonstrate the three representations:

A + B Infix notation

+ AB Prefix or Polish notation

AB + Postfix or reverse Polish notation

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• The reverse Polish notation is in a form suitable for stack manipulation. The expression

A • B + C • D

is written in reverse Polish notation as

AB • CD • +

Evaluation of Arithmetic Expressions

• The following numerical example may clarify this procedure. Consider the arithmetic expression

(3 * 4) + (5 * 6)

In reverse Polish notation, it is expressed as

34 • 56 • +

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Operation

• Each box represents one stack operation and the arrow always points to the top of the stack.
• Scanning the expression from left to right, we encounter two operands. First the number 3 is pushed into the stack, then the number 4.
• The next symbol is the multiplication operator • .
• This causes a multiplication of the two topmost items in the stack.
• The stack is then popped and the product is placed on top of the stack, replacing the two original operands.
• Next we encounter the two operands 5 and 6, so they are pushed into the stack.
• The stack operation that results from the next • replaces these two numbers by their product.
• The last operation causes an arithmetic addition of the two topmost numbers in the stack to produce the final result of 42.

Instruction Formats

• The format of an instruction is usually depicted in a rectangular box symbolizing the bits of the instruction as they appear in memory words or in a control register.
• The most common fields found in instruction formats are:

1. An operation code field that specifies the operation to be performed.

2. An address field that designates a memory address or a processor register.

3. A mode field that specifies the way the operand or the effective address is determined

• Most computers fall into one of three types of CPU organizations:
• 1. Single accumulator organization.
• 2. General register organization.
• 3. Stack organization

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• An example of an accumulator-type organization is the basic computer presented in previous Chap.
• All operations are performed with an implied accumulator register. The instruction format in this type of computer uses one address field.
• For example, the instruction that specifies an arithmetic addition is defined by an assembly language instruction as
• A D D X

• An example of a general register type of organization…….
• The instruction format in this type of computer needs three register address fields. Thus the instruction for an arithmetic addition may be written in an assembly language as
• A D D R 1 , R 2 , R 3

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• The stack-organized CPU was presented in Fig. 8-4. Computers with stack organization would have PUSH and POP instructions which require an address field.

Thus the instruction

• P U S H X

Three-Address Instructions

Two-Address Instructions

One-Address Instructions

Zero-Address Instructions

Addressing Modes

• The way the operands are chosen during program execution is dependent on the addressing mode of the instruction.
• The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually referenced.

1. To give programming versatility to the user by providing such facilities as pointers to memory, counters for loop control, indexing of data, and program relocation.

2. To reduce the number of bits in the addressing field of the instruction