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Suhas Vittal¹

Poulami Das²

Moinuddin Qureshi¹

Towards Adaptive Leakage Suppression

for Fault-Tolerant Quantum Computing

ERASER

International Symposium on Microarchitecture (MICRO), 2023

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2

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Quantum Applications Need Low Error Rates

Hardware errors create a gap between applications and devices.

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2023

2026

203X

~400 qubits

p = 0.5%

~4000 qubits

p = 0.1%

~100K qubits

p = 0.01%

Goal

Applications-at-scale

p < 10^-10

Significant gap in error rates!

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A Primer on Quantum Error Correction

QEC can detect errors on data qubits by measuring parity checks.

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Z

X

Parity Checks (Stabilizers)

Bit flips (X)

Phase flips (Z)

Surface Code Logical Qubit

Z

Data

Z Syndrome Extraction

M+R*

Syndrome: 01001000

Parity Check Fails

*(M+R = Measure + Reset)

One way to close this gap is via quantum error correction, where we encode one fault-tolerant logical qubit using many constituent physical qubits. This logical qubit is encoded using the surface code, which protects qubits

With a combination of two parity checks between four qubits.. The first type of parity check is a
Z stabilizer, which detects bit flip, or X errors.
The second type of parity check is an X stabilizer, which detects phase flip, or Z, errors.
Each stabilizer has a corresponding parity qubit, and
To measure these checks, we must execute a quantum circuit known as a syndrome extraction circuit to measure these parity qubits.
Upon executing this circuit, we obtain a bitstring known as a syndrome.
By analyzing a syndrome, we can infer what errors have occurred on the data qubits.

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Error Correction with the Surface Code

The surface code is resilient against typical errors on quantum computers.

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X

Z

Y

X Errors

Z Errors

Y Errors

CNOT and Meas. Errors

Round 3

Round 2

Round 1

01100010

00001010

00010000

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1

Z

M+R

Data

Meas.

CNOT

By leveraging both types of parity checks, the surface code can detect many common errors. Let’s first look at data qubit errors.
Any X error on the logical qubit will flip at most two Z stabilizers, and
Any Z error will flip at most two X stabilizers.
If we have a Y error, which is an X and Z error at the same, we can detect this as well since this will flip all parity qubits next to a data qubit.
However, as quantum operations are also erroneous, we may have CNOT and measurement errors.
To handle these errors, we perform syndrome extraction to get multiple rounds of syndromes.
Then, we can distinguish CNOT and measurement errors from data qubit errors, so the surface code can detect such errors as well.
So, we can handle arbitrary data qubit errors and operation errors. Is there anything we cannot handle?

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Other Errors on The Surface Code

Leakage errors are an obstacle to quantum fault-tolerance.

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Type of Error	Error Rate

Decoherence

p

CNOT and Measurement

Leakage

0.1p

Circuit-Level

Error Model

Code Distance d

(Redundancy)

Logical Error Rate

Circuit-Level Model

With leakage

Undetectable!

Gates stop working!

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Outline

Quantum Errors and Error Correction

Leakage and Leakage Reduction Circuits

ERASER: Results

ERASER: Insights and Design

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How and why do qubits leak?

How do leakage errors affect quantum systems?

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|q>

|0>

|1>

|2>

|3>

Operations are calibrated here.

Higher energy states (leakage)

Two-Qubit Operations (CNOTs)

Environmental Effects (Heating)

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Leakage Errors Cause Other Errors

Leakage errors induce random parity flips during syndrome extraction.

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|L>

or

X, Y, Z

Depolarizing Error

|L>

or

Leakage Transport

|L>

Z

Q

Error from Q	Z Flips?

I or Z

X or Y

Leakage Transport

No

Yes

50/50

Leakage errors introduce random errors into the quantum systems through CNOTs.

The leaked qubit causes the CNOT to malfunction, resulting in a random error on the other qubit involved in the CNOT. For the purposes of this presentation, this is a random Pauli error, or I, X, Y, or Z error. Such errors are known as depolarizing errors.
Another possibilitiy is where
The leaked qubit transports some of its leakage to the other qubit.
This is known as a leakage transport.
Let’s look at how a leaked data qubit Q can affect a Z stabilizer, which corrects bit flip, or X errors.
If Q causes an I or Z error, these do not flip the Z stabilizer.
If Q causes an I or Y error, these flip the Z stabilizer as they cause a bit flip.
Finally, a leakage transport can result in a flip when measuring, as leaked qubits result in a random measurement outcome.

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Leakage Reduction Circuits (LRCs)

With Always-LRCs Scheduling, we can periodically remove leakage.

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(P)

|L>

M + R

Standard

With LRCs

M+R

(D)

|L>

Always-LRCs Schedule:

No LRC

LRC

No LRC

LRC

...

Round 1

Round 2

Round 3

Round 4

W

S

W

A

P

S

W

A

P

So, how can we correct leakage? Let’s first start with normal syndrome extraction, where

Leakage errors on data qubits persist across rounds.
However, leakage errors on parity qubits are easily removed by the reset at the end of the circuit.
To deal with data qubit leakage, prior work has proposed leakage reduction circuits, or LRCs. These LRCs SWAP a data qubit and a parity qubit and then measure and reset the data qubit. If there is no leakage error, the circuit performs normal syndrome extraction.
If there is a leakage error, then the SWAP fails and the data qubit is reset, removing any data qubit leakage.
However, if a parity qubit has a leakage error, then that error persists even after the LRC.
Given that LRCs remove data qubit leakage and no LRCs remove parity qubit leakage, state-of-the-art LRC scheduling, or Always-LRCs scheduling schedules LRCs every other round to periodically protect both data and parity qubits.

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Leakage Transport with LRCs

LRCs facilitate leakage transport via extra 2-qubit operations.

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M+R

|L>

M+R

|L>

Transport Probability: 10%

Transport Probability: 34%

3 CNOTs

LRC

No LRC

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Impact of Leakage Transport on LRCs

LRCs increase leakage due to leakage transport. What do we do?

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Syndrome Extraction Rounds

Leakage Population

No LRC

LRC

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Goal: Minimize the Errors Caused by LRCs

We propose ERASER to achieve this goal.

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Problem: Using LRCs too aggressively causes leakage to accumulate due to leakage transport.

This is a prediction problem!

Always-LRCs: 24 LRCs/round

Optimal: 1/3 LRCs/round

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Outline

Quantum Errors and Error Correction

Leakage and Leakage Reduction Circuits

ERASER: Results

ERASER: Insights and Design

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When should we use an LRC?

Insight: Use LRCs whenever parity checks fail.

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All syndromes

all have zeros.

Do not use an LRC!

No Error

Leakage

Error

Not

Leakage

Handled by the stabilizers

Handled by LRCs

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Challenges with Adaptively Using LRCs

Insight: We should optimize for visible leakage, which is most common.

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Z

X

Z

L

The only information about leakage are the syndromes measured each round.

# of Flips	Prob.

0

1

2

3

4

6%

25%

38%

25%

6%

94% of leakage

(“visible”)

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When should we use LRCs?

Insight: Too conservative or aggressive scheduling increases error.

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0000

0001

0110

No LRC

Possible Errors

T1/T2

M

|L>

Too Many LRCs

Too Few LRCs

Lowest Error:

ERASER default

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ERASER’s Timing Constraints

ERASER computes LRC decisions within 120ns.

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M+R

30ns

120ns

Syndrome

Speculate whether to use LRC

Decision!

LRC

No LRC

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A Thousand Feet View of ERASER

ERASER adaptively schedules LRCS while meeting all design constraints.

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Flips ≥ 2

A

Needs LRC

B

C

M+R

Skip

Add

<1% FPGA Utilization

Latency is a few ns

Prediction

Assignment

Scheduling

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A First Look at ERASER’s Performance

How can we further improve ERASER?

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4x

6x

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ERASER-M: Using Multi-Level Discriminators

ERASER-M uses multi-level discriminators to improve the logical error rate.

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0

1

2-Level

Discriminator

M

|L>

0 or 1

0

1

L

Multi-Level

Discriminator

M

L

|L>

LRC

M+R

R

|L>

Preemptively handle leakage transport

Minimize LRC gate error

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A Case for Multi-Level Discriminators

ERASER-M improves upon ERASER by leveraging additional leakage info.

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ERASER

0

1

L?

???

Syndromes provide incomplete info!

0

1

L

2-Level

Discriminator

Multi-Level

Discriminator

|L>

LRC

M + R

R

|L>

ERASER-M

Now, how can we improve ERASER’s ability to remove leakage.

Currently, ERASER only uses a standard 2-level discriminator, so
Leaked qubits always yield a random measurement. Thus, ERASER can only
Rely on the syndromes to speculate leakage.
However, if we had access to a multi-level discriminator so qubits can be measured as leaked, we can make scheduling modifications to better suppress errors.
First, if we measure a parity qubit as leaked, we can schedule all of its neighboring data qubits for LRCs in case there was leakage transport.
Second, if we measure a data qubit as leaked during an LRC, we can skip the upcoming SWAP gate and replace it with parity qubit reset.
We call this extension of ERASER ERASER-M, and ERASER-M
Better suppresses leakage by leveraging the additional information granted by multi-level discrimination.

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Outline

Quantum Errors and Error Correction

Leakage and Leakage Reduction Circuits

ERASER: Results

ERASER: Insights and Design

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Results: Leakage Population Ratio

ERASER significantly improves LPR compared to Always-LRCs.

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Leakage Population Ratio (LPR)

“amount of leakage at any point in time”

Distance 11 Surface Code

2.2x

2.1x

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What about the Logical Error Rate (LER)?

ERASER significantly improves LER compared to Always-LRCs.

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4.3x

6x

Over 10 QEC Cycles (10d rounds)

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Why does ERASER perform well?

ERASER performs well by judiciously using LRCs.

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Speculation Accuracy

“Are we only using LRCs when there is data qubit leakage?”

No Leakage

Leakage

Policy	False Pos. Rate
Always-LRCs	50%
ERASER	3%
ERASER-M	3%

Policy	False Neg. Rate
Always-LRCs	25%
ERASER	50%
ERASER-M	40%

99% of Cases

1% of Cases

ERASER Overall Accuracy: 97%

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Conclusion

1. Suppressing leakage is necessary to achieve quantum fault-tolerance.

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2. We use leakage reduction circuits (LRCs) to remove leakage from data qubits by resetting them every other round

ERASER demonstrates that adaptively scheduling LRCs improves the logical error rate significantly over naïve LRC scheduling.

3. Leakage is not the common case, so using LRCs frequently is counterproductive as it can introduce new leakage.

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A Challenger Approaches...

Leakage must be suppressed to achieve fault-tolerance.

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L

Leakage Errors

Code cannot fix it!

Gates stop working!

Hard to distinguish!

Code Distance d

(Redundancy)

Logical Error Rate

No leakage

With leakage

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Comparing Always-LRCs to Optimal-LRCs

How can we identify when data qubits have leakage?

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Always-LRCs

No LRC

LRC

No LRC

LRC

No LRC

LRC

No LRC

Optimal-LRCs

No LRC

LRC

No LRC

|L>

No LRC

LRC

No LRC

LRC

|L>

Leakage errors must be removed ASAP.

|L>

No LRC

LRC

No LRC

LRC

Do not use LRCs unnecessarily.

|L>

No LRC

First, we quickly recap different scheduling strategies.

We have already discussed Always-LRCs, whose pitfall is that the aggressive use of LRCs can introduce errors due to leakage transport. Always-LRCs is not the best scheduling policy.
On the other hand, Optimal LRCs is an idealized policy that
removes leakage only when it occurs. Even though the LRC circuit is susceptible to leakage transport, Optimal LRCs minimizes this problem through conservative scheduling and is thus desirable.
However, scheduling is not as simple as just using fewer LRCs.
Leakage errors cause random errors during syndrome extraction if they are not removed.
Thus, as soon as a data qubit leakage error occurs, we need to use an LRC.
Also, using LRCs when there is no data qubit leakage can introduce additional errors.
Thus, we should avoid using LRCs when no data qubits are leaked.
Now, we need to figure out how to identify when data qubits are leaked.

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Using Syndromes to Speculate Leakage

ERASER schedules an LRC for a data qubit where nearby parity qubits flip.

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Can flip 0-4 parity qubits

Z

X

Z

# of Flips	Prob With No Leakage	Prob. With Leakage
0	99.6%	6%
1	0.4%	25%
2	(very low)	38%
3	(very low)	25%
4	(very low)	6%

L?

P(flips > 0 when there is leakage) = 94%

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Why does ERASER perform well?

ERASER improves performance by using LRCs judiciously.

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Common Case is No Leakage

97% Accuracy

Speculation Accuracy

“Are we only using LRCs when there is data qubit leakage?”

Hard-to-Detect Leakage (few bit flips)