8086
Microprocessor
Case Study: Intel Processors
Slide 2
Microproce ssor
Third Generation
During 1978 HMOS technology ⇒ Faster speed, Higher
packing density 16 bit processors ⇒ 40/ 48/ 64 pins
Easier to program Dynamically relatable programs Processor has multiply/ divide arithmetic
hardware More powerful interrupt handling
capabilities
Flexible I/O port addressing
Intel 8086 (16 bit processor)
First Generation
Between 1971 – 1973 PMOS technology, non compatible with TTL
4 bit processors ⇒ 16 pins
8 and 16 bit processors ⇒ 40 pins Due to limitations of pins, signals are
multiplexed
Second Generation
During 1973
NMOS technology ⇒ Faster speed, Higher density, Compatible with TTL
4 / 8/ 16 bit processors ⇒ 40 pins Ability to address large memory spaces and I/O ports
Greater number of levels of subroutine nesting
Better interrupt handling capabilities
Intel 8085 (8 bit processor)
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
32 bit processors
Physical memory space 224 bytes = 16 Mb Virtual memory space 240 bytes = 1 Tb Floating point hardware
Supports increased number of addressing modes
Intel 80386
Fifth Generation Pentium
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Overview
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8086 Microprocessor
First 16- bit processor released by
INTEL in the year 1978
manufactured
Originally HMOS, now using HMOS III technique
Approximately 29, 000 transistors, 40
pin DIP, 5V supply
Does not have internal clock; external asymmetric clock source with 33% duty cycle
20-bit address to access memory ⇒ can
220
address up to = 1 megabytes of memory space.
Addressable
memory space is organized in to two banks of 512 kb each; Even (or lower) bank and Odd (or higher) bank. Address line A0 is used to select even bank and control signal 𝐁𝐇𝐄 is used to access odd bank
Uses a separate 16 bit address for I/O mapped devices ⇒ can generate 216 = 64 k addresses.
Operates in two modes: minimum mode and maximum mode, decided by the signal at MN and 𝐌𝐗 pins.
Pins and Signals
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8086 Microprocessor
Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these are
multiplexed with data.
When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A0-A15.
When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These are multiplexed with status signals
Pins and Signals
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8086 Microprocessor
Common signals
BHE (Active Low)/S7 (Output)
Bus High Enable/Status
It is used to enable data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7.
MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the
processor is to operate in.
RD (Read) (Active Low)
The signal is used for read operation.
It is an output signal. It is active when low.
Pins and Signals
8086 Microprocessor
Common signals
TEST
𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’
instruction.
8086 will enter a wait state after execution of the WAIT instruction and will resume execution only when the
𝐓𝐄𝐒𝐓 is made low by an active hardware.
This is used to synchronize an external activity to the processor internal operation.
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The signal is active high.
READY
This is the acknowledgement from the slow device or memory that they have completed the data transfer.
The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086.
Pins and Signals
8086 Microprocessor
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Common signals
RESET (Input)
Causes the processor to immediately
terminate its present activity.
The signal must be active HIGH for at
least four clock cycles.
CLK
The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle.
INTR Interrupt Request
This is a triggered input. This is sampled during the last clock cycles of each instruction to determine the availability of the request. If any interrupt request is pending, the processor enters the interrupt acknowledge cycle.
This signal is active high and internally
synchronized.
Min/ Max Pins
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Pins and Signals
8086 Microprocessor
The 8086 microprocessor can work in two modes of operations : Minimum mode and Maximum mode.
In the minimum mode of operation the microprocessor do not associate with any
co-processors multiprocessor
and can not be used for systems.
In the maximum mode the 8086 can work in multi-processor or co-processor configuration.
Minimum or maximum mode operations
are decided by the pin MN/ MX(Active low).
When this pin is high 8086 operates in minimum mode otherwise it operates in Maximum mode.
Pins and Signals
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8086 Microprocessor
Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied
to VCC (logic high)
8086 itself generates all the bus control signals
DT/𝐑ഥ | (Data Transmit/ Receive) Output signal from the processor to control the direction of data flow through the data transceivers |
𝐃𝐄𝐍 | (Data Enable) Output signal from the processor used as out put enable for the transceivers |
ALE | (Address Latch Enable) Used to demultiplex the address and data lines using external latches |
M/𝐈𝐎 | Used to differentiate memory access and I/O access. For memory reference instructions, it is high. For IN and OUT instructions, it is low. |
𝐖𝐑 | Write control signal; asserted low Whenever processor writes data to memory or I/O port |
𝐈𝐍𝐓𝐀 | (Interrupt Acknowledge) When the interrupt request is accepted by the processor, the output is low on this line. |
Minimum mode signals
Pins and Signals
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8086 Microprocessor
HOLD | Input signal to the processor form the bus masters as a request to grant the control of the bus. Usually used by the DMA controller to get the control of the bus. |
HLDA | (Hold Acknowledge) Acknowledge signal by the processor to the bus master requesting the control of the bus through HOLD. The acknowledge is asserted high, when the processor accepts HOLD. |
Minimum mode signals
Pins 24 -31
For minimum mode operation, the MN/ 𝐌𝐗 is tied
to VCC (logic high)
8086 itself generates all the bus control signals
Pins and Signals
12
8086 Microprocessor
During maximum mode operation, the MN/ 𝐌𝐗 is grounded (logic low)
Pins 24 -31 are reassigned
𝑺𝟎, 𝑺𝟏, 𝑺𝟐 | Status signals; used by the 8086 bus controller to generate bus timing and control signals. These are decoded as shown. |
Maximum mode signals
Pins and Signals
13
8086 Microprocessor
During maximum mode operation, the MN/ 𝐌𝐗 is grounded (logic low)
Pins 24 -31 are reassigned
𝑸𝑺𝟎, 𝑸𝑺𝟏 | (Queue Status) The processor provides the status of queue in these lines. The queue status can be used by external device to track the internal status of the queue in 8086. The output on QS0 and QS1 can be interpreted as shown in the table. |
Maximum mode signals
Pins and Signals
14
8086 Microprocessor
During maximum mode operation, the MN/ 𝐌𝐗 is grounded (logic low)
Pins 24 -31 are reassigned
𝐑𝐐/𝐆𝐓𝟎, 𝐑𝐐/𝐆𝐓𝟏 | (Bus Request/ Bus Grant) These requests are used by other local bus masters to force the processor to release the local bus at the end of the processor’s current bus cycle. These pins are bidirectional. The request on𝐆𝐓𝟎 will have higher priority than𝐆𝐓𝟏 |
𝐋𝐎𝐂𝐊 | An output signal activated by the LOCK prefix instruction. Remains active until the completion of the instruction prefixed by LOCK. The 8086 output low on the 𝐋𝐎𝐂𝐊 pin while executing an instruction prefixed by LOCK to prevent other bus masters from gaining control of the system bus. |
Maximum mode signals
8086 Microprocessor
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Architecture
Architecture
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8086 Microprocessor
Execution Unit (EU)
EU executes instructions that have already been fetched by the BIU.
BIU and EU functions separately.
Bus Interface Unit (BIU)
BIU fetches instructions, reads data from memory and I/O ports, writes data to memory and I/ O ports.
Bus Interface Unit (BIU)
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Architecture
8086 Microprocessor
Dedicated Adder to generate 20 bit address
Four 16-bit segment
registers
Code Segment (CS) Data Segment (DS) Stack Segment (SS) Extra Segment (ES)
Segment Registers >>
Architecture
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8086 Microprocessor
Sl.No. | Type | Register width | Name of register |
1 | General purpose register | 16 bit | AX, BX, CX, DX |
8 bit | AL, AH, BL, BH, CL, CH, DL, DH | ||
2 | Pointer register | 16 bit | SP, BP |
3 | Index register | 16 bit | SI, DI |
4 | Instruction Pointer | 16 bit | IP |
5 | Segment register | 16 bit | CS, DS, SS, ES |
6 | Flag (PSW) | 16 bit | Flag register |
8086 registers categorized into 4 groups
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | | OF | DF | IF | TF | SF | ZF | | AF | | PF | | CF |
Architecture
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8086 Microprocessor
Register | Name of the Register | Special Function |
AX | 16-bit Accumulator | Stores the 16-bit results of arithmetic and logic operations |
AL | 8-bit Accumulator | Stores the 8-bit results of arithmetic and logic operations |
BX | Base register | Used to hold base value in base addressing mode to access memory data |
CX | Count Register | Used to hold the count value in SHIFT, ROTATE and LOOP instructions |
DX | Data Register | Used to hold data for multiplication and division operations |
SP | Stack Pointer | Used to hold the offset address of top stack memory |
BP | Base Pointer | Used to hold the base value in base addressing using SS register to access data from stack memory |
SI | Source Index | Used to hold index value of source operand (data) for string instructions |
DI | Data Index | Used to hold the index value of destination operand (data) for string operations |
Registers and Special Functions
Bus Interface Unit (BIU)
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Architecture
8086 Microprocessor
Segment Registers
8086’s 1-megabyte memory is divided into segments of up to 64K bytes each.
Programs obtain access to code and data in the segments by changing the segment register content to point to the desired segments.
The 8086 can directly address four segments
(256 K bytes within the 1 M byte of memory) at a particular time.
Bus Interface Unit (BIU)
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Architecture
8086 Microprocessor
Segment Registers
Code Segment Register
16-bit
CS contains the base or start of the current code segment; IP contains the distance or offset from this address to the next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically shifting the contents of CS 4-bits to the left and then adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the contents of the CS register multiplied by 16 and then offset is added provided by the IP.
Bus Interface Unit (BIU)
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Architecture
8086 Microprocessor
Segment Registers
Data Segment Register
Bus Interface Unit (BIU)
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Architecture
8086 Microprocessor
Segment Registers
Stack Segment Register
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the Stack Segment (SS) and the Stack Pointer (SP) for stack instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack address is calculated from the Stack segment (SS) and the Base Pointer (BP).
Bus Interface Unit (BIU)
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Architecture
8086 Microprocessor
Segment Registers
Extra Segment Register
Bus Interface Unit (BIU)
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Architecture
8086 Microprocessor
Segment Registers
Instruction Pointer
16-bit
Always points to the next instruction to be executed within
the currently executing code segment.
So, this register contains the 16-bit offset address pointing to the next instruction code within the 64Kb of the code segment area.
Its content is automatically incremented as the execution
of the next instruction takes place.
Bus Interface Unit (BIU)
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Architecture
8086 Microprocessor
A group of First-In-First- Out (FIFO) in which up to
6 bytes of instruction code are pre fetched from the memory ahead of time.
This is done in order to
speed up the execution
overlapping fetch with
by instruction execution.
This mechanism is known
as pipelining.
Instruction queue
Execution Unit (EU)
Architecture
8086 Microprocessor
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Some of the 16 bit registers can be used as two 8 bit registers as :
AX can be used as AH and AL BX can be used as BH and BL CX can be used as CH and CL DX can be used as DH and DL
EU decodes and executes instructions.
A decoder in the EU control system translates instructions.
16-bit ALU for performing arithmetic and logic operation
Four general purpose
registers(AX, BX, CX, DX);
Pointer registers (Stack
Pointer, Base Pointer);
and
Index registers (Source Index, Destination Index) each of 16-bits
Execution Unit (EU)
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Architecture
8086 Microprocessor
EU
Registers
Accumulator Register (AX)
Consists of two 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word, and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting / outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or AL.
Execution Unit (EU)
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Architecture
8086 Microprocessor
EU
Registers
Base Register (BX)
Consists of two 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word, and BH contains the high-order byte.
This is the only general purpose register whose contents can be used for addressing the 8086 memory.
All memory references utilizing this register content for addressing use DS as the default segment register.
Execution Unit (EU)
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Architecture
8086 Microprocessor
EU
Registers
Counter Register (CX)
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of
the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the
contents of CX as a counter.
Example:
The instruction LOOP START automatically decrements CX by 1 without affecting flags and will check if [CX] = 0.
If it is zero, 8086 executes the next instruction; otherwise the 8086 branches to the label START.
Execution Unit (EU)
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Architecture
8086 Microprocessor
EU
Registers
Data Register (DX)
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.
When combined, DL register contains the low order byte of
the word, and DH contains the high-order byte.
Used to hold the high 16-bit result (data) in 16 X 16 multiplication or the high 16-bit dividend (data) before a 32 ÷ 16 division and the 16-bit reminder after division.
Execution Unit (EU)
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Architecture
8086 Microprocessor
EU
Registers
Stack Pointer (SP) and Base Pointer (BP)
SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during execution of instructions that involve the stack segment in the external memory.
SP contents are automatically updated (incremented/ decremented) due to execution of a POP or PUSH instruction.
BP contains an offset address in the current SS, which is used by instructions utilizing the based addressing mode.
Execution Unit (EU)
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Architecture
8086 Microprocessor
EU
Registers
Source Index (SI) and Destination Index (DI)
Used in indexed addressing.
Instructions that process data strings use the SI and DI registers together with DS and ES respectively in order to distinguish between the source and destination addresses.
Execution Unit (EU)
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Architecture
8086 Microprocessor
EU
Registers
Source Index (SI) and Destination Index (DI)
Used in indexed addressing.
Instructions that process data strings use the SI and DI registers together with DS and ES respectively in order to distinguish between the source and destination addresses.
Architecture
8086 Microprocessor
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Flag Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| | | | OF | DF | IF | TF | SF | ZF | | AF | | PF | | CF |
Carry Flag
This flag is set, when there is a carry out of MSB in case of addition or a borrow in case of subtraction.
Parity Flag
This flag is set to 1, if the lower byte of the result contains even number of 1’s ; for odd number of 1’s set to zero.
Auxiliary Carry Flag
This is set, if there is a carry from the lowest nibble, i.e, bit three during addition, or borrow for the lowest nibble, i.e, bit three, during subtraction.
Zero Flag
This flag is set, if the result of the computation or comparison performed by an instruction is zero
Sign Flag
This flag is set, when the result of any computation is negative
Tarp Flag
If this flag is set, the processor enters the single step execution mode by generating internal interrupts after the execution of each instruction
Interrupt Flag
Causes the 8086 to recognize external mask interrupts; clearing IF disables these interrupts.
Direction Flag
This is used by string manipulation instructions. If this flag bit is ‘0’, the string is processed beginning from the lowest address to the highest address, i.e., auto incrementing mode. Otherwise, the string is processed from the highest address towards the lowest address, i.e., auto incrementing mode.
Over flow Flag
This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large enough to accommodate in a destination register. The result is of more than 7-bits in size in case of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations, then the overflow will be set.
Execution Unit (EU)
ADDRESSING MODES
& Instruction set
Introduction
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8086 Microprocessor
Program
A set of instructions written to solve
a problem.
Instruction
Directions which a microprocessor follows to execute a task or part of a task.
Computer language
High Level
Low Level
Machine Language
Assembly Language
◼ Binary bits
◼ English Alphabets
◼ ‘Mnemonics’
◼ Assembler
Mnemonics → Machine
Language
ADDRESSING MODES
Addressing Modes
Group I : Addressing modes for
register and immediate data
| Group II : Addressing modes for memory data |
| Group III : Addressing modes for I/O ports |
11. Relative Addressing | Group IV : Relative Addressing mode |
12. Implied Addressing | Group V : Implied Addressing m4o0de |
8086 Microprocessor
Every instruction of a program has to operate on a data. The different ways in which a source operand is denoted in an instruction are known as addressing modes.
1. Register Addressing
2. Immediate Addressing
THANK YOU
COURSE: DCN UNIT: 1
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