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Design & Benchmark of Pulsed Latch

Group Members :

  • Animesh Sharma (MT20317 )
  • Naman Shukla (MT 20166)
  • Shakti Shrey (MT20323)

Group Number: 18

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Design Specifications

Specifications

Values

Technology

65 nm

Supply voltage

1.2 Volts

Clock frequency

500 MHz

Output Load

20 fF

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Design Schematic

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Simulation Waveforms

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Latch Action

Pulse Generator Action

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Stick diagram (Moving to Layout )

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Initial Layout (Un-Optimized)

Lay-out Area = 16.2 u-m-square

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Final Layout (Optimizations in Area)

4.93 u-m

2.40 u-m

Lay-out Area = 11.83 u-m- square

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Final Layout (On removing PP & NP Layers)

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DRC & LVS Verification

DRC Clean!

LVS Matched!

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Pre-layout Timings: Set-up & Hold Characterization

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T-setup = -53.75 ps @ SS/1.08v/-40

T-hold = 89.96 ps @ FF/1.32/125

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Simulation Results : Timing Characterizations

Parameter

PRE-LAYOUT

POST-LAYOUT

T-setup

SS/1.08v/-40 : -53.75 ps

SS/1.08v/-40: -48 ps

T-hold

FF/1.32V/125: 89.96s

FF/1.32V/125: 91 ps

T-dq

SS/1.08/-40: 234 ps

FF/1.32/125: 134 ps

SS/1.08/-40: 300 ps

FF/1.32/125: 167 ps

T-cq

SS/1.08/-40: 270 ps

FF/1.32/-40: 128 ps

SS/1.08/-40: 349 ps

FF/1.32/125: 139 ps

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Power Calculations :

Parameters

PRE-LAYOUT

POST-LAYOUT

CLK Duty cycle

10%

25%

50%

10%

25%

50%

P-dynamic �(TT/1.2V/25C)

8.4 uW

11.2 uW

17 uW

10uW

14.1 uW

20.4 uW

Leakage (FF/1.32V/125C)

0.129 uW

0.135 uW

CLK Capacitance

​

4 fF

10 fF

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Observations , Learnings & Contributions

  • We observed the importance of Stack Inverters in producing Clock pulse of sufficient width, such that with proper sizing of devices in latch, we are able to latch input to the output within clock pulse width with proper delays.
  • We learned about calculation of Set-up, hold timings and Power on Eldo and Area Optimizations in the Standard Cell Layout.
  • All the work has been done mutually ---
  • Initial Study : Done Mutually.
  • Schematic & Simulations : Naman Shukla & Mahesh Kumar
  • Stick diagram, Layout & Optimizations : Animesh Sharma & Shakti Shrey

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References

  • S. N. Dwivedi, A. K. Seth and A. Grover, "Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption," 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020, pp. 1-6, doi: 10.1109/VDAT50263.2020.9190213.
  • Neil H. E. Weste, David Money Harris “CMOS VLSI Design : A circuits and systems perspective
  • H. Karimiyan Alidash, S. M. Sayedi and H. Saidi, "Low-power state-retention dual edge-triggered pulsed latch," 2010 18th Iranian Conference on Electrical Engineering, 2010, pp. 417-420, doi: 10.1109/IRANIANCEE.2010.5507035.
  • Jan M. Rabaey. 1996. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, Inc., Upper Saddle River, NJ.