BRANCH-E&TC ENGINEERING

SEM – 4^th

SUBJECT-Analog Electronics & Linear IC

CHAPTER-03- FIELD EFFECT TRANSISTOR

TOPIC- FET

Ay-2021-2022 ,summer-2022

FACULTY-ER S MOHANTA.(Hod e & tc engg Dept)

FET X BJT (NPN)

Gate

Drain

Source

Base

Collector

Emitter

FET

• 3 terminal device
• Channel e^- current from source to drain controlled by the electric field generated by the gate
• Extremely high input impedance for base

BJT

• 3 terminal device emitter to collector e^- current controlled by the current injected into the base

Types of FETs

• In addition to carrier type (N or P channel), there are differences in
• how the control element is constructed (Junction x Insulated) and
• those devices must be used differently

• depletion/enhancement mode
• enhancement mode

(insulated gate FETs, IGFETs, are the same as MOSFETs)

Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross section. Typically L = 1 to 10 μm, W = 2 to 500 μm, and the thickness of the oxide layer is in the range of 0.02 to 0.1 μm.

Waterfalls analogy

( a ) MOSFET in the linear region

( b ) MOSFET with channel just pinched

off at the drain.

( c ) Channel pinch off for v_DS > v_GS - V_TN

Water

The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

An NMOS transistor with v_GS > V_t and with a small v_DS applied. The device acts as a conductance whose value is determined by v_GS. Specifically, the channel conductance is proportional to v_GS - V_t, and this i_D is proportional to (v_GS - V_t) v_DS. Note that the depletion region is not shown (for simplicity).

Linear Region (small v_DS)

v_GS ≥ V_tn

0 ≤ v_DS ≤ v_DSSAT= v_GS-V_tn

V_TN =1V

Operation of the enhancement NMOS transistor as v_DS is increased. The induced channel acquires a tapered shape and its resistance increases as v_DS is increased. Here, v_GS is kept constant at a value > V_t.

The drain current i_D versus the drain-to-source voltage v_DS for an enhancement-type NMOS transistor operated with v_GS > V_t.

Output characteristics�for an NMOS transistor with�V_tn = 1 V and k’_n (W/L)= 25 x 10^-6 A/V²

v_D ≥ v_S

Derivation of the i_D - v_DS characteristic of the NMOS transistor.

The PMOS Transistor

Output characteristics for a �PMOS transistor with�V_tp = -1V and k’_P (W/L)= 25 x 10^-6 A/V²

v_S ≥ v_D

Cross section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.

(a) An n-channel enhancement-type MOSFET with v_GS and v_DS applied and with the normal directions of current flow indicated. (b)The i_D - v_DS characteristics for a device with V_t = 1 V and k’_n(W/L) = 0.5 mA/V² (d) The i_D - v_GS characteristic for an enhancement-type NMOS transistor in saturation.

(d)

Channel Length Modulation

L_M

Increasing v_DS beyond v_DSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by ΔL).

Effect of v_DS on i_D in the saturation region. The MOSFET parameter V_A is typically in the range of 30 to 200 V.

Output Resistance:

V_A is directly proportional to L; thus two devices with the same process, and having channel lengths L₁ e L₂, will have Early voltage V_A1 and V_A2,.

Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance r_o. The output resistance models the linear dependence of i_D on v_DS and is given by r_o ≅ V_A/I_D.

Summary of equations for the enhancement-mode MOSFET

P-channel

N-channel

V_tn > 0

v_DS ≥ 0

V_tp < 0

v_DS ≤ 0

or

or

The current-voltage characteristics of a depletion-type n-channel MOSFET for which V_t = -4 V and k’_n(W/L) = 2 mA/V²: �(a) transistor with current and voltage polarities indicated; (b) the i_D - v_DS characteristics; (c) the i_D - v_GS characteristic in saturation.

Bias Circuits 1

• λ usually neglected ( 1/ λ =V_A→∞)
• Q-point most often located in saturation for analog circuits

( assuming the MOSFET to be

in the saturation region )

( two solutions → only one

is possible )

Ex: V_DD = 10 V R₁ = 150 kΩ R₂ = 100 kΩ R_S = 10 kΩ

R_D = 50 kΩ k’_n(W/L) = 50 μA/V² V_t = 1 V

​

Solution: I_D = 100 μA V_DS = 4 V

Bias Circuits 2

Two power supplies are

available

A simple circuit utilizing �a current source

Analysis

Basic MOSFET current mirror.

Q₁: I → V converter

Q₂: V → I converter

If Q₂ in saturation

​

​

then

Example: V_DD = 5V ;I_REF=10μA; Q₁ and Q₂ are matched ; L=10 μm and W=100 μm; V_t = 1V ;

k^’_n=20 μ A/V² V_A = 10L; ΔVo=+3V

The operation of the MOSFET as an amplifier.

Small-signal models for the MOSFET: (a) neglecting the dependence of i_D on v_DS in saturation (channel-length modulation effect); and (b) including the effect of channel-length modulation modeled by output resistance r_o = |V_A|_/I_D.

(a.1) π-Model

(a.2) T-Model

(b.1) π-Model

(b.2) T-Model

Example: V_t = 1.5V ; k^’_n(W/L)=0.25 mA/V² V_A = 50V

Small-signal equivalent-circuit model of a MOSFET in which the body is not connected to the source.

Basic amplifier configurations with current sources

Source follower

or common-drain

amplifier

Common-source

amplifier

Common-gate

amplifier

The CMOS common-source amplifier: (a) circuit; (b) i-v characteristic of the active-load Q₂; (c) graphical construction to determine the transfer characteristic; and transfer characteristic.

I_D2

I_D2

Example: V_DD=10V;V_tn = | V_tp| = 1V ; k^’_n= 2 k^’_p= 20 μA/V² �(W=100 μm; L =10 μm |V_A|= 100V for both the n and p device)�I_REF=100 μA.

The CMOS common-gate amplifier: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the circuit in (b).

The source follower: (a) circuit; (b) small-signal equivalent circuit; and (c) simplified version of the equivalent circuit.

THANK YOU