Quantitative Analysis and Digital Logic
What is Performance?
For now, when we say performance, we mean response time or execution time.
Important Factors
CPU Execution Time | Seconds CPU spent executing a sequence of instructions |
Instruction Count | Number of instructions executed |
Cycles Per Instruction (CPI) | Average number of clock cycles required per instruction |
Clock Cycle Time | Seconds per clock cycle (reciprocal of clock frequency) |
How Are These Factors Related?
How Are These Factors Related?
Sanity Check
# instructions
(cycles/instruction)
(seconds/cycle)
Processor | Clock Rate | CPI |
P1 | 3.0 GHz | 1.5 |
P2 | 2.5 GHz | 1.0 |
P3 | 4.0 GHz | 2.2 |
Note that the reciprocal of cycles per instruction is instructions per cycle.
(cycles / second)*(instructions / cycle) = instructions / second
(clock rate) / (CPI) = instructions / second
P1: | 3.0 | GHz | / | 1.5 | = | 2 | billion | instructions | / | second |
P2: | 2.5 | GHz | / | 1.0 | = | 2.5 | billion | instructions | / | second |
P3: | 4.0 | GHz | / | 2.2 | = | 1.82 | billion | instructions | / | second |
Processor | Clock Rate | CPI |
P1 | 3.0 GHz | 1.5 |
P2 | 2.5 GHz | 1.0 |
P3 | 4.0 GHz | 2.2 |
(clock rate) * (cpu time) = number of cycles
P1: | 3.0 | GHz | * | 10 | seconds | = | 30 | billion | cycles |
P2: | 2.5 | GHz | * | 10 | seconds | = | 25 | billion | cycles |
P3: | 4.0 | GHz | * | 10 | seconds | = | 40 | billion | cycles |
(number of cycles) / (cycles per instruction) = number of instructions
P1: | 30 | billion | cycles | / | 1.5 | = | 20 | billion | instructions |
P2: | 25 | billion | cycles | / | 1.0 | = | 25 | billion | instructions |
P3: | 40 | billion | cycles | / | 2.2 | = | 18.18 | billion | instructions |
Processor | Clock Rate | CPI |
P1 | 3.0 GHz | 1.5 |
P2 | 2.5 GHz | 1.0 |
P3 | 4.0 GHz | 2.2 |
old cpu time = (instruction count * CPI) / clock rate
new cpu time = (instruction count * 1.2 * CPI) / (x * clock rate)
new cpu time / old cpu time = 0.7 (1.2/x)/1 = 1.2/x = 0.7
0.7x = 1.2
x = 1.2/0.7 = 1.714
P1: 5.14 GHz
P2: 4.29 GHz
P3: 6.86 GHz
Amdahl’s Law
A
B
Total Execution Time E
| A/s | B |
New Total Execution Time E’
Amdahl’s Law
f*E
(1-f)*E
Total Execution Time E
| (f*E)/s | (1-f)*E |
New Total Execution Time E’
Amdahl’s Law
f*E
(1-f)*E
Total Execution Time E
| (f*E)/s | (1-f)*E |
New Total Execution Time E’
Amdahl’s Law
f*E
(1-f)*E
Total Execution Time E
| (f*E)/s | (1-f)*E |
New Total Execution Time E’
The new execution time is 94.4% of the old execution time. The execution time has reduced by 5.6%.
The execution time has improved by a factor of 1.06x.
The new execution time is 84% of the old execution time. The execution time has reduced by 16%.
The execution time has improved by a factor of 1.19x.
Digital Logic
Binary Addition Review
0101
+ 0111
????
1101
+ 1111
????
Binary Addition Review
| 0101 | | 1101 |
+ | 0111 | + | 1111 |
1100
1|1100
Cannot be expressed using four bits (overflow)
Making an Adder
Add
A
B
A+B
Making an Adder
Add
A
B
A+B
A | B | A+B |
0 | 0 | ? |
0 | 1 | ? |
1 | 0 | ? |
1 | 1 | ? |
Making an Adder
Add
A
B
A+B
A | B | A+B |
0 | 0 | 0 |
0 | 1 | 1 |
1 | 0 | 1 |
1 | 1 | 10 |
Making an Adder
Add
A
B
A+B
A | B | C | S |
0 | 0 | 0 | 0 |
0 | 1 | 0 | 1 |
1 | 0 | 0 | 1 |
1 | 1 | 1 | 0 |
Making an Adder
Add
A
B
A+B
A | B | C | S |
0 | 0 | 0 | 0 |
0 | 1 | 0 | 1 |
1 | 0 | 0 | 1 |
1 | 1 | 1 | 0 |
Making an Adder
Add
A
B
A+B
A | B | C | S |
0 | 0 | 0 | 0 |
0 | 1 | 0 | 1 |
1 | 0 | 0 | 1 |
1 | 1 | 1 | 0 |
Half Adder
A
B
A+B
A | B | C | S |
0 | 0 | 0 | 0 |
0 | 1 | 0 | 1 |
1 | 0 | 0 | 1 |
1 | 1 | 1 | 0 |
Adding with a Carry
A | B | Cin | Cout | S |
0 | 0 | 0 | 0 | 0 |
0 | 0 | 1 | 0 | 1 |
0 | 1 | 0 | 0 | 1 |
0 | 1 | 1 | 1 | 0 |
1 | 0 | 0 | 0 | 1 |
1 | 0 | 1 | 1 | 0 |
1 | 1 | 0 | 1 | 0 |
1 | 1 | 1 | 1 | 1 |
Full Adder
https://microcontrollerslab.com/cd4008-4-bit-full-adder-ic-pinout-features-example-datas heet/
4-bit Ripple Carry Adder