The Israeli Systems & AI Workshop (ISAI) 2026
The Evolution of AI:
A Compute Story
Adi Fuchs, PhD�NVIDIA
“FROM VACUUM TUBES TO HETEROGENEOUS SILICON SYSTEMS"
SAFE HARBOR
The Evolution of AI · A Compute Story
DISCLAIMER:
THIS TALK DOES NOT REPRESENT NVIDIA
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This presentation reflects my independent research and personal views.
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It was prepared independently and is not sponsored, endorsed, or otherwise affiliated with NVIDIA or any of my current or former employers.
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ISAI 2026 · ADI FUCHS
ACT I · THE QUESTION
ISAI 2026 · 01 / 10
The Evolution of AI · A Compute Story
THE DAWN OF THINKING MACHINES
AI has been with us a LONG time ago …
1950–1958
The Turing Test: “Can Machines Think?”
Dartmouth Workshop: McCarthy, Minsky, Shannon, and Rochester. Coined the term: “Artificial Intelligence”
Rosenblatt's Perceptron: a learning machine built from motors, wires and 400 photocells.
1950
1956
1958
… BUT compute was NOT.
ACT I · THE BOTTLENECK
The Evolution of AI · A Compute Story
The Ideas Were There,
But Scale Was NOT
THE ALGORITHMS EXISTED. COMPUTE CAPABILITIES DID NOT MATCH.
1960s compute ceiling
CDC 6600
10 MFLOPS peak
HYPOTHETICAL SINGLE-MACHINE TRAINING TIME · LOG SCALE
10³
10⁴
10⁵
10⁶
10⁷
10⁸
10⁹
YEARS
COMPUTER VISION
AlexNet · ImageNet 2012
4.7×10¹⁷ FLOPs
1.5K y
1.45 GFLOPs/image × 1.2M × 90 × 3
MACHINE TRANSLATION
Transformer-base · WMT14
3.3×10¹⁸ FLOPs
10.5K y
reported training cost · Vaswani et al.
IMAGE GENERATION
DDPM-CIFAR · 2020
3.8×10¹⁸ FLOPs
12.1K y
reconstructed U-Net count · 12.42G × 128 × 800K × 3
IMAGE GENERATION
DiT-XL/2 · ImageNet 256²
6.4×10²⁰ FLOPs
2.0M y
118.6 GFLOPs × 256 × 7M × 3
Sources: CHM CDC 6600 (1964) · Krizhevsky et al. (2012) · Vaswani et al. (2017) · Ho et al. (2020) · Peebles & Xie (2023)
IPhone 17
2.5 TFLOPs peak
250,000x faster!!
ACT X · THE OUTCOME
The Evolution of AI · A Compute Story
The Outcome: AI Winters
PROMISES OUTRAN CAPABILITY
The field did not disappear. The funding did.
1969
1974
1987
FIRST WINTER · 1974–1980
× Perceptrons as general intelligence
The XOR limitation (Minsky & Papert's 1969) read as a verdict on neural nets.
× Rule-based machine translation
ALPAC (1966) found progress below the promised payoff; funding receded.
SECOND WINTER · 1987–1993
× Expert systems
Useful in narrow domains; brittle and costly to update outside encoded knowledge.
× Lisp machines · Fifth Generation
Cheaper workstations won; Japan's 11-year project closed in 1992 without the expected commercial impact.
Sources: Lighthill (1973) · ALPAC (1966) · Minsky & Papert (1969) · House of Lords AI Committee · ICOT / Fifth Generation Computer Systems
Lesson: Hype Creates Investment. Capabilities Sustain it.
ACT II · LEARNING AT SCALE
The Evolution of AI · A Compute Story
WHEN DATA CENTERS LEARNED TO SEE
Computer Vision: NNs First Trained On Distributed CPUs
2000s–2012
01
2000s — statistical ML wins with hand-crafted features.
02
2012 — Google DistBelief scales a neural net across a CPU cluster.
03
10M unlabeled YouTube frames → one neuron learns “cat.”
04
The result is still CPU-bound: 16K cores, 1B parameters, 3 days.
Deep learning's brief CPU-cluster era · 2012
16,000
CPU CORES ACROSS 1,000 MACHINES
1 billion
PARAMETERS — LARGEST NET OF ITS DAY
3 days
TO TRAIN — AND STILL CPU-BOUND
ACT III · THE GPU BIG BANG
The Evolution of AI · A Compute Story
AlexNet: When GPUs Started The Deep Learning Era
2012
01
AlexNet wins ImageNet 2012 with a 15.3% top-5 error.
02
THE MAGIC: First Implementation of CNNs on
massively-parallel GPUs (Two NVIDIA GTX 580s)
03
A 60M-parameter CNN trainable in 5–6 days, not years.
04
Slashed the error of state-of-the-art solutions by almost half
Source: Krizhevsky et al. (2012), Abstract + Tables 1–2. 2010 and 2012 values are shown as separate competition groups.
ACT IV · BREAKING THE SERIAL CHAIN
ISAI 2026 · 05 / 10
The Evolution of AI · A Compute Story
Language: Transformers Broke the Serial Bottleneck
1997 → 2017 · state encoding meets parallel context
01
RNN / LSTM encode the past in a rolling state hₜ.
02
The bottleneck: hₜ cannot exist before hₜ₋₁.
03
Longer sequences mean longer chains — less parallelism.
04
Transformers encode context in parallel with all-to-all attention.
RNN / LSTM · STATE ENCODING
Hochreiter & Schmidhuber, 1997
TRANSFORMER · CONTEXT IN PARALLEL
Vaswani et al., 2017
ATTENTION · PARALLEL “ALL-TO-ALL” PROCESSING
THE PAYOFF
12 hours · 8 P100 GPUs
significantly more parallelization
Sources: Hochreiter & Schmidhuber(1997) · Vaswani et al. (2017), §1, Table 1, Figures 1 & 3
GPUS · AGAIN – THE ENABLERS
Vaswani et al., 2017
Vaswani et al., 2017
ACT V · THE AGE OF SCALING LAWS
ISAI 2026 · 06 / 10
The Evolution of AI · A Compute Story
01
Scaling laws: loss falls as model size, tokens. and FLOPs grow.
02
Frontier training compute grows ~4.4× per year (Epoch AI).
03
GPT-4, Gemini Ultra, Grok 4 now reach 10²⁵–10²⁶ FLOPs.
04
Bitter Lesson: scale wins over human eng; but at what costs?
THE DOWNSTREAM PROBLEM
“That’s going to take new economic models or much cheaper inference to get wider spread.”
— Sam Altman, OpenAI Forum (2026)
SCALING LAWS · KAPLAN ET AL. (2020)
EPOCH AI · TRAINING COMPUTE (FLOP)
4.4× / year
Sources: Kaplan et al. (2020), Figure 1 · Epoch AI, “Training compute of notable models” · Touvron et al. (2023), LLaMA Figure 1 · arXiv:2302.13971 · Sam Altman, OpenAI Forum (2026)
Scaling Laws: More Parameters, More Data, More Compute
THE TRILLION
DOLLAR PAPER
ACT VI · THE SPECIALIZATION TURN
ISAI 2026 · 07 / 11
The Evolution of AI · A Compute Story
THE HARDWARE PRECEDENT FOR SPARSE EXPERTS
01
Dennard Scaling that powered >50y of CMOS scaling stopped working.
02
Transistors multiplied; full-chip power rose as S².
03
At 80 W budget, usable silicon fell 17.6% → 6.5% → 3.3%.
04
The response: specialized circuitry, each built for a hot path.
THE UTILIZATION WALL A.K.A DARK SILICON
You can pack more transistors, but can’t power them.
The solution: specialize the data path, use the transistors you have more efficiently!
CONSERVATION CORES · FULL-DIE POWER
300 mm² die · full frequency
full-chip power (watts)
DARK SILICON · % OF CHIP OFF
22 nm: 21% off → 8 nm: >50% off
Power rose 5.3×; usable silicon fell 5.3×.
SPECIALIZED SILICON · C-CORES
general CPU vs. CPU with specialized cores
More capacity, less active compute — the same trick is coming to the model.
Sources: Venkatesh et al. (2010), Table 2 & Fig. 1 · Esmaeilzadeh et al. (2011), Fig. 4 · Fedus et al. (2022)
Dark Silicon: Silicon Lessons From Unsustainable Scaling
ACT VI · THE SPECIALIZATION TURN
ISAI 2026 · 08 / 11
The Evolution of AI · A Compute Story
MoE: Dark Silicon Lesson Applied to AI Models
DENSE MODELS CANNOT KEEP PAYING FOR EVERY TOKEN.
WE NEED TO SPECIALIZE THE DATAPATH FOR AI MODELS LIKE WE DID FOR CHIPS!
MODEL-SCALE SPARSITY
DENSE MODEL
MIXTURE OF EXPERTS
t1
t2
t3
FULL BLOCK 1
FULL BLOCK 2
FULL BLOCK 3
FULL BLOCK 4
100% of the stack is activated for every token.
t1
t2
t3
R
EXPERT 1
EXPERT 2
EXPERT 3
EXPERT 4
1 of N experts is active per token.
A modern LLM would consist of many experts, each specializing at a subset of problems,
much like an SoC consists of HW accelerators, each specializing at a subset of problems
AI-SILICON PARALLEL FUTURE:
ACT VII · THE INFERENCE ERA
The Evolution of AI · A Compute Story
2025 DISAGGREGATED SERVING
Serving LLMs: the Prefill / Decode split
PREFILL · BUILD THE CONTEXT
Computes all to all attention from the input.
Builds the KV Cache (Context)
Writes to memory only once
Highly parallel. Compute Heavy. Bandwidth Light.
REQUEST
prompt
prefill
KV cache
decode
DECODE · AUTOREGRESSIVE PREDICTION
Generates one token at a time.
Append KV pair to context. Then, predict next token.
Weights + KV cache move each step.
Inherently serial. Compute Light.
Bandwidth Heavy.
.
KV CACHE HANDOFF
PREFILL POOL
DECODE POOL
TWO PHASES. TWO SYSTEMS. TWO PROPERTIES
ACT VI · A CAMBRIAN EXPLOSION OF SILICON
The Evolution of AI · A Compute Story
ONE WORKLOAD, MANY MACHINES
2016–NOW
The GPU won the war — so specialization began. No one size fits all
LLM serving is also enabled by hardware – a slew of heterogenous chips
Google TPU
Systolic matrix array — dense matmul at datacenter scale.
Cerebras WSE
Wafer-scale: ~4T transistors, 900k cores, no off-chip wall. High bandwidth and compute. But limited capacity, GOOD FOR DECODE
Groq LPU
Deterministic dataflow, all-SRAM — record decode latency. High bandwidth.�Limited capacity. GOOD FOR DECODE
SambaNova RDU
Reconfigurable dataflow — the chip reshapes to the model. Three-tiered memory architecture.
DMatrix
Massive MIMD with memory next to every core
AWS Trainium
Networking-first silicon built to scale training out. High parallelism, lower bandwidth – GOOD FOR PREFILL
The GPU won the war — so specialization began: dataflow, wafer-scale, and SRAM machines each attack a different bottleneck.
The right phase should run on the right silicon
ACT VIII · AGENTIC AI
The Evolution of AI · A Compute Story
THE AGENTIC LOOP: STARTED AROUND LATE 2025
Agentic AI: CPUs are back!
A SINGLE REQUEST
GPU / Accelerator
dense tensor math
CPU
control, tools, glue logic
Memory & Storage
KV-cache, retrieval, state
Network
the fabric binding it all
GPU · CPU · MEMORY · NETWORK
Agentic AI: from simply inferring to tool calling
Sending tokens as inputs, parsing program outputs as tokens
Most programs still run on CPUs, and we also need CPUs for orchestration
From 4-8:1 GPU to CPU ratio, we are back at 1:1 or even 1:2 (more CPUs!)
2012-2018
2021-2025
2023-
2024-
2025-
ACT X · THE NEXT FRONTIER
What’s next for AI?
History has taught us: new AI frontiers will always require new means of compute
The Evolution of AI · A Compute Story
LET’S CONTINUE THE CONVERSATION
The Evolution of AI · A Compute Story
Adi Fuchs