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VHDL 101

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Finite state machines with datapath

ABC of FSMD

Online at http://bit.ly/vhdl101-06a

José Manuel Martins Ferreira | josemmf@usn.no

Professor | Fakultet for Teknologi, Naturvitenskap og Maritime Fag | https://www.usn.no

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Learning outcomes

After watching this presentation you should be able to:

  • Explain what is is the distinctive features of finite state machines with datapath
  • Explain how the data path plus control path architecture can be adapted to represent a binary multiplier and a minimal architecture CPU

josemmf@usn.no | VHDL 101

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Outline of this presentation

  • What’s a finite state machine with datapath?
  • Example: Binary multiplication
  • Example: Minimal CPU

josemmf@usn.no | VHDL 101

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What is a FMSD?

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Distinctive features

  • A FSMD is one level of complexity above a FSM
  • It comprises a FSM that works as a controller, and a diversity of other blocks that make up a data path
  • FSMD are used widely used in the implementation of systems described at RT-level (manipulating and transferring data among several registers)

josemmf@usn.no | VHDL 101

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FSMD architecture

josemmf@usn.no | VHDL 101

FSM

Data

unit 1

Data

unit 2

Data

unit 3

Data

unit 4

control path

data path

The control�path receives �information from

and provides control to the data units

status

commands

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Example: A binary multiplier

josemmf@usn.no | VHDL 101

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Binary multiplier

  • Block diagram of a binary multiplier FSMD that works by adding one of the operands to itself as many times as the other operand (5 x 3 = 5 + 5 + 5)

josemmf@usn.no | VHDL 101

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josemmf@usn.no | VHDL 101

+

Adder register

FSM

Down counter

2

2

load

decrement

clear

update

update

zero

Output register

din_A

din_B

dout

data path

control path

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Example: A minimal CPU

josemmf@usn.no | VHDL 101

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Stored-program computer

  • The minimal number of blocks consists of:
    • An instruction register to hold the instruction code
    • A program counter to address the memory
    • A data register to perform operators
    • An instruction decoder and execution control unit

josemmf@usn.no | VHDL 101

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josemmf@usn.no | VHDL 101

DR

PC

load IR

incr PC

load DR

incr DR

memory data bus

memory address bus

IR

Instruction

decoder and control

data path

control path

out bus

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Thanks for

your attention

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