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Chapter 2

Open Chiplet Economy

OCP Sponsored Tutorial

Chiplet Summit Feb 6^th 2024

1:00 pm to 5:00 pm

Santa Clara California, USA

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The Open Chiplet Economy:�Driven by the OCP

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What Our Volunteers Delivered in 2023

Q1	The Open Chiplet Economy (at the Chiplet Summit) Chiplets business workshop (to be repeated) Bunch of Wires 2.0
Q2	Link Layer 1.0 ODSA Breakout Session at the OCP Regional Summit
Q3	OCP-LBL Chiplets Workshop JEDEC JEP30 Part Model standard (seeded/driven by OCP CDXML)
Q4	PHY workshop (to be repeated) First ever open chiplet economy experience center – real chiplets, workflow, IP MRHIEP Manufacturing Roadmap Final Report Packaging analysis paper at VLSI Design Conference ODSA Breakout Session at OCP Global Summit

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OCP/ODSA Contribution to Standards/Tools�Engineer-Driven Multi-company Efforts

Area	Output
D2D PHY	Bunch of Wires 1.0 Bunch of Wires 2.0 2.1 in flight	1^st standard to scale from laminate to advanced packaging, 2-32 Gbps/lane Known implementations in 65, 22, 16, 12, 7, 6, 5, 4, 3nm – true heterogeneity 10+ products in flight Proven power of 0.3 to 0.5 pJ/bit, support for proprietary extensions
D2D Spreadsheet	V3.0 in flight	Biennial release compares data on all PHYs
D2D Link and Transaction	TLP 1.0	Only known “streaming mode” open link layer
D2D Transaction Profile	NXP DiPort/Other Profiles	Only known open maps of AXI SOC Traffic to D2D PHYs
CDX	JEDEC JEP30 PM Open 3DK	Standard for physical chiplet description Workflow white papers
Business	Chiplet cost model Business white paper	Open spreadsheet model to compare chiplet/mono Product planning assistance document
Prototyping	Test Package	1^st open package to integrate chiplets across vendors Fully open package design and analysis Aim to build a common bring up infra First demo of chiplets/IP/workflow from 11 companies in an experience center

All specifications available without an NDA, can be used without any restrictions

10+ refereed conference and journal papers

Community-driven hyperscale innovation for all.

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Building a Chiplet

Choose a target market
Choose a function (CPU, I/O, Memory, Accelerator…)
Choose a packaging technology
Choose an interface PHY standard
Choose an information transfer protocol
Design chiplet
Is that enough for standalone commercial product success?
Not clear that it is, successful products have been built as families.

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One Example – designing D2D bandwidth�(Classification From Elad Alon BCA)

Category	Package	Per-Line Rate	Termination	Reach
Ultra Wide (UW)	Advanced only�(<55 μm pitch)	< 8 Gb/s	No	<4mm
Ultra Dense (UD)	Advanced only�(40-55 μm pitch)	8 – 32 Gb/s	No	<2mm
Full Reach (FR)	Standard or fanout�(55-130 μm pitch)	< 40 Gb/s	Supported	<25mm
Cost-Optimized �Full Reach �(CO-FR)	Low-layer standard�(130-180 μm pitch)	< 40 Gb/s	Supported	<25mm

Die Edge

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Bandwidth vs. Bump Density, Even within a Standard

From Elad Alon at Blue Cheetah�OCP Global Summit

Options at a performance target

The exact way to achieve a�combination of power,

performance, packaging �technology is and will need

to be domain-specific

Already true at the �Hyperscalers

Every chiplet your chiplet

talks to has to make the same�trade-offs your chiplet made

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Reduce Friction in Chiplet Integration�Bring Factors Forward in Design

Customer�Specification

Design &�Verification

Semiconductor�Foundry

Assembly�Packaging & Test

System�Software

OEM and�Product

codesign

physical modularity

Function modularity

additional constraints �with chiplets

Factors brought forward or made more complex

Functional modularity – partition function across chiplets. Manage design and production.
Physical modularity – allocate power, size, stress budgets
Codesign – low-level software and new functionality has to recognize existing partition

Large companies solve this by building chiplets in families and with engineering convention

https://www.opencompute.org/blog/building-an-open-chiplet-economy

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Large Companies Design Chiplets in Families

Area	Candidates
D2D PHY	UCIe, BoW, SuperChips, XSR
D2D Transactions	CXL, ODSA TLP, DiPort
Chiplet and package test	IEEE 1838
Chiplet description	OCP-JEDEC CDXML
Power models	ISIL
Device traceability	SEMI
Size guardrails	🗶
Power delivery guardrails	🗶
Thermal guardrails	🗶
Wiring density guardrails	🗶
Mechanical guardrails	🗶
Bump and assembly pitch	🗶

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Fugaku Thought Experiment

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2/6/2024

Attribute	Detail
Die size/ Power/Thermals	Approximately 400 mm²/�122 W/0.3 W per mm²
Aspect ratio	20x20
Cores/ASIC	52
Tofu, /HBM/PCIe/ area power	Tofu 25 mm²/9W, 100 mm² for 4 HBM + 1 PCIe
Ring bus extra area	Approximately 35 mm², 10 mm²/complex
Core complex	Approximately 240 mm², 60 mm²/complex
Core Area/Power	4.6 mm²/2.2W
Fab/Process	TSMC/7 nm Finfet
ASICs/Node	2
Nodes/System	158,976
System power	40 MW

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1st We Chipletize into Standardized Modules

Community-driven hyperscale innovation for all.

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Then We Create a Family of Variants

Community-driven hyperscale innovation for all.

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Please join us in 2024

Modular architectures
Workflows

Tools to catalog chiplets,
Design kits for chiplet workflows

Reference Implementations

Develop shared infrastructure e.g. bring-up

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