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What is a transistor?

Silicon is a metalloid: it isn’t a great conductor
Need to add charge carriers by "doping", and apply an electric field

N-type: floating (-) (electrons)
P-type: floating (+) (electron holes - bubbles)

Semiconductor charge carrier animation

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Conceptual drawing

Source = Drain, just labels
Polysilicon: conductor

Was metal (metal oxide semiconductor field effect transistor, MOSFET)

SiO2: insulator
Gate produces electric field

Attracts electrons/holes to form an electrically conductive channel
Some turn on at zero gate voltage, others turn off (enhancement mode / depletion mode)

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Taps: avoid forward bias

Keep the substrate neutral, avoid latchup

Polysilicon: transistor

Backward slash

Metal: conductor

Forward slash

SiO2: insulator

Solid gray

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3-input NAND

Top - parallel P-MOS
Bottom - series N-MOS

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Challenge - Signal Degradation

Not a problem with pure CMOS

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Unrelated

–but cool– Example

A*B C*D (A*B)+(C*D)

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Fabrication - Photolithography

Photolithography steps to form N-Well:

https://www.youtube.com/watch?v=POCuBW7xRUs

Photolithography steps to form CMOS transistor:

https://www.youtube.com/watch?v=OBiu2agne_U

Semiconductor manufacturing economics summary:

https://twitter.com/TubeTimeUS/status/1352676882920083457

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Spacing guidelines (ca 2004, academic)

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4-NAND TTL 7400 chip

First built circa 1964

10ns switching, 4 gates/chip

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ARM1 chip from 1985

25,000 transistors for a 32-bit CPU

Parts of the ARM1 by Ken Shirriff

ARM1 gate-level simulation in WebGL

by Visual6502

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M1 Ultra, 2022 ARM chip

114 billion transistors at 5nm process

20-core CPU (3.2 & 2.0 GHz), 64-core GPU,

and 32-core Neural Engine (32 trillion ops/sec)

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Making things 70 atoms wide is hard

Unsolved lithography issues at 7nm (== about 70 atoms)

Extreme Ultraviolet (EUV) light transmission requires a hard vacuum
Focusing light on the order of a wavelength requires computational lithography (essentially computational holography)
Electron beam measuring features can limit fabrication throughput
Machine-specific aberrations might need machine-specific lithography masks
Photon shot noise: shorter wavelength -> more energy/photon -> fewer photons
Literally getting a few atoms out of place can make the circuit fail

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Lithography: Victim of its own Success?

Transistor scaling means you can make either:

The same transistors for a lower price (preferred by microcontrollers)
More transistors for the same price (preferred by Intel)

Power scaling is slower than area scaling, so we can build more transistors than we can afford to switch every cycle ("dark silicon crisis").

We have no idea how to productively write code to use billions of transistors.

More registers, arithmetic units, or cores are typically not needed (and burn power).
Pre-bake in dedicated ASICs for most conceivable tasks?
Bigger caches? Deeper branch prediction? Rent out chip area for ads?