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14 of 111

We need you!

SymbiFlow!

j.mp/lca19-symbiflow

15 of 111

Compare� software toolchain...

j.mp/lca19-symbiflow

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Software Tooling

Compiler

Java

Software

C++

Software

Ada

Software

j.mp/lca19-symbiflow

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Software Tooling

Frontend

+

Generic�Optimization

x86 Backend

ARM Backend

MIPS Backend

Java

Software

C++

Software

Ada

Software

j.mp/lca19-symbiflow

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C++ Tooling for x86

Frontend

+

Generic�Optimization

x86 Backend

ARM Backend

MIPS Backend

Java

Software

C++�Software

Ada�Software

j.mp/lca19-symbiflow

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C++ Tooling for x86

Java

Software

C++ Software

Ada�Software

Frontend +

Generic�Optimization

x86 Backend

ARM Backend

MIPS Backend

C++

file

C++

file

binary

asm

Compile

j.mp/lca19-symbiflow

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EDA Tooling Ecosystem

FPGA Tools

ASIC Tools

Verification, Testing, �& Simulation

Synthesis

Tools

VHDL

Hardware

Verilog

Hardware

SystemVerilog

Hardware

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Verilog Tooling for FPGAs

Verilog Hardware

Synthesis

Tools

FPGA Backend

Verilog

file

Verilog

file

binary

fasm

Compile

ASIC Tools

VHDL

Hardware

SystemVerilog

Hardware

Verification, Testing, �& Simulation

j.mp/lca19-symbiflow

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Verilog Tooling for FPGAs

SymbiFlow toolchain!

Verilog Hardware

Synthesis

Tools

FPGA Backend

MIPS Backend

Verilog

file

Verilog

file

binary

fasm

Compile

ASIC Tools

VHDL

Hardware

SystemVerilog

Hardware

j.mp/lca19-symbiflow

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"GCC" for FPGAs!

j.mp/lca19-symbiflow

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What does "GCC" mean?

Not C/C++ → Verilog

j.mp/lca19-symbiflow

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What does "GCC" mean?

Not C/C++ → Verilog

Fully Free & Open Source
Cross-platform + Multi-platform
Pluggable / Interchangeable

j.mp/lca19-symbiflow

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SymbiFlow

Toolsuite

j.mp/lca19-symbiflow

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How did we�get here?

j.mp/lca19-symbiflow

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First Project IceStorm

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Yosys

arachne-pnr

Project�IceStorm

j.mp/lca19-symbiflow

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Then Project X-Ray

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Yosys

Project�X-Ray

Project�IceStorm

arachne-pnr

j.mp/lca19-symbiflow

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Started SymbiFlow

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Yosys

Project�X-Ray

Project�IceStorm

arachne-pnr

j.mp/lca19-symbiflow

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SymbiFlow Launch - 34C3!

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

Yosys

Project�X-Ray

Project�IceStorm

Architecture Definitions

arachne-pnr

j.mp/lca19-symbiflow

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Inspires Project Trellis

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

Yosys

Project�X-Ray

Project�Trellis

Project�IceStorm

Architecture Definitions

arachne-pnr

j.mp/lca19-symbiflow

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Launches nextpnr

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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SymbiFlow Toolsuite

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Parts of

SymbiFlow

j.mp/lca19-symbiflow

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SymbiFlow Toolsuite

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

A quick summary of the projects are;

* Bitstream documentation projects for Lattice iCE40 (the existing Project IceStorm), Xilinx Series 7 FPGAs (Project X-Ray - https://symbiflow.github.io/prjxray-db/) and Lattice ECP5 (Project Trellis - https://symbiflow.github.io/prjtrellis-db/). This could be considered the "binutils" type part of the toolchain -- the final part which takes assembly and converts it into a binary object you can load onto an actual device.

* The "SymbiFlow Architecture Definitions" repository which can be found at https://github.com/SymbiFlow/symbiflow-arch-defs (were the majority of the current work is currently going). This repository is for describing the internals of an FPGA for use by the place-and-route tools. In many ways this is an "executable documentation" project and you can think of it like describing the registers and other properties of a normal machine. In some ways it is kind of like "device tree" in Linux.

* The "synthesis and mapping tool" for which we are reusing Yosys (https://github.com/YosysHQ/yosys). You can think of this as the frontend part of a compiler (the bit which parses the language side -- IE C or Ada or Fortran).

* The place and route tools which we have two separate efforts on. You can can think of as the "compiler toolchain backend" that actually generates the assembly code. The two independent efforts are;

* nextpnr - https://github.com/YosysHQ/nextpnr

* Verilog to Routing - https://verilogtorouting.org/

It is unclear which of the two tools we will adopt as the primary place-and-route effort in the long term. Both tools can **already** be used to target the existing iCE40 FPGA and both tools are making progress towards non-trivial designs on larger FPGA.

Does that help? All this information will eventually end up on the website as things get closer to being more user focused and less "getting shit to work" focussed :-)

37 of 111

Bitstream Docs

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Place and Route

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Synthesis & Mapping

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Architecture Defs

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Related to Bitstream

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Feeds Place & Route

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Feeds Mapping (?)

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Verilog Simulation

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Executable Docs

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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SymbiFlow

Status

j.mp/lca19-symbiflow

47 of 111

SymbiFlow Toolsuite

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Bitstream Docs

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Status

bitstream docs

j.mp/lca19-symbiflow

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Bitstream Summary

Project�X-Ray

Project�Trellis

Project�IceStorm

More?

Advanced Tiles

- DSP

- Hard Blocks

- Clock Tiles

- IO Tiles

Routing

- Logic

- Clock

Basic Tiles

- Logic

- Block RAM

☑�☑ ☑

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j.mp/lca19-symbiflow

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Lattice iCE40

Project IceStorm

Supported Devices

iCE40 LP
iCE40 LM (some)
iCE40 HX
iCE40 UltraPlus

Future Supported?

iCE40 Ultra
iCE40 UltraLite

Documented Tiles Types

Logic
Block RAM
IO
Hard IP Blocks
Single Port RAM
DSP

Current Documentation

Bitstream
Verilog Models

Still needed

Replacement for�Tech Libraries

Database - www.clifford.at/icestorm

Documentation - www.clifford.at/icestorm

Source Code - github.com/cliffordwolf/icestorm

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Lattice ECP5

Project Trellis

Supported Devices

ECP5 U Series�LFE5U-25F, LFE5U-45F, LFE5U-85F
ECP5 UM Series�LFE5UM-25F, LFE5UM-45F, LFE5UM-85F
ECP5 UM5G Series�LFE5UM5G-25F, �LFE5UM5G-45F, LFE5UM5G-85F

Future?

Crosslink Series?

Documented Tiles Types

Logic
Interconnect
Clocks
Block RAM
IO
PLL
DSP
SERDES
IOLOGIC

Current Documentation

Bitstream
Verilog Models

Still needed

Replacement for�Tech Libraries

Database - symbiflow.github.io/prjtrellis-db

Documentation - prjtrellis.readthedocs.org

Source Code - github.com/SymbiFlow/prjtrellis

Mailing List - lists.librecores.org/listinfo/prjtrellis

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Lattice ECP5

Project Trellis

Supported Devices

ECP5 U Series�LFE5U-25F, LFE5U-45F, LFE5U-85F
ECP5 UM Series�LFE5UM-25F, LFE5UM-45F, LFE5UM-85F
ECP5 UM5G Series�LFE5UM5G-25F, LFE5UM5G-45F, LFE5UM5G-85F

Future?

Crosslink Series?

Documented Tiles Types

Logic
Interconnect
Clocks
Block RAM
IO
PLL
DSP
SERDES
IOLOGIC

Current Documentation

Bitstream
Verilog Models

Still needed

Replacement for�Tech Libraries

Database - symbiflow.github.io/prjtrellis-db

Documentation - prjtrellis.readthedocs.org

Source Code - github.com/SymbiFlow/prjtrellis

Mailing List - lists.librecores.org/listinfo/prjtrellis

j.mp/orc-ecp5

j.mp/lca19-symbiflow

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Xilinx Series 7

Project X-Ray

Supported Devices

Artix 7�XC7A50T (15T, 35T)
Kintex 7�XC7K70T

Future?

All Artix 7
All Kintex 7
All Virtex 7
All Zynq (?)

Documented Tiles Types

Full

Logic (SLICEL)
Distributed RAM (SLICEM)
Routing

Partial

Block RAM
IOB

Need help!

Hard Blocks
DSP

Current Documentation

Bitstream
Verilog Models

Still needed

Replacement for�Tech Libraries

Database - symbiflow.github.io/prjxray-db

Documentation - prjxray.readthedocs.org

Source Code - github.com/SymbiFlow/prjxray

Mailing List - lists.librecores.org/listinfo/prjxray

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Artix 7 50T

Xilinx Series 7

Project X-Ray

j.mp/lca19-symbiflow

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Artix 7 50T

Xilinx Series 7

Project X-Ray

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Xilinx Series 7

Project X-Ray

Name	Unused		Unknown	Known		Total
CLBLL_l	58	2.51%	0	2246	100.00%	2304
CLBLL_r	58	2.51%	0	2246	100.00%	2304
CLBLM_l	46	2.51%	0	2258	100.00%	2304
CLBLM_r	46	2.51%	0	2258	100.00%	2304
HCLK_l	580	50.35%	0	572	100.00%	1152
HCLK_r	580	50.35%	0	572	100.00%	1152

Slice L (Logic)

Slice M (Logic + Distributed Memory)

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Bitstream Summary

Project�X-Ray

Project�Trellis

Project�IceStorm

More?

Advanced Tiles

- DSP

- Hard Blocks

- Clock Tiles

- IO Tiles

Routing

- Logic

- Clock

Basic Tiles

- Logic

- Block RAM

☑�☑ ☑

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☒ ☒ ☒ ☑

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j.mp/lca19-symbiflow

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Xilinx xc20xx

Project 2064

Supported Devices

XC2018�100 tiles!
XC2064�64 tiles!

Documented Tiles Types

Full

Logic
RAM
Routing
IOB

Current Documentation

Bitstream

Still needed

Verilog Models
Replacement for�Tech Libraries
Timing documentation

Database - TBD

Documentation - TBD

Source Code - github.com/JohnDMcMaster/project2064

Mailing List - lists.librecores.org/listinfo/symbiflow

"The XC 2064 logic cell array is available

now at a unit price of $55 to $80 …

The Xilinx XACT development system is

available now at a price of $12,000."

j.mp/lca19-symbiflow

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Bitstream Summary

☑�☑ ☑

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Project�X-Ray

Project�Trellis

Project�IceStorm

Project�2064

Advanced Tiles

- DSP

- Hard Blocks

- Clock Tiles

- IO Tiles

Routing

- Logic

- Clock

Basic Tiles

- Logic

- Block RAM

More?

j.mp/lca19-symbiflow

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Bitstream Summary

Project�X-Ray

Project�Trellis

Project�IceStorm

Project�2064

Advanced Tiles

- DSP

- Hard Blocks

- Clock Tiles

- IO Tiles

Routing

- Logic

- Clock

Basic Tiles

- Logic

- Block RAM

☑�☑ ☑

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☒ ☒ ☒ ☑

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More?

☑�☑ ☑

☑

☑ ☑ ☑ ☑

☑

☑ ☑

You can help!

j.mp/lca19-symbiflow

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Bitstream Summary

We need you!

Xilinx

Spartan 6
Spartan 3

Altera

????????

j.mp/lca19-symbiflow

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Status

Synthesis & Mapping & PnR

j.mp/lca19-symbiflow

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Synthesis & Mapping & PnR

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

j.mp/lca19-symbiflow

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Synthesis & Mapping & PnR

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

Both using Yosys!

j.mp/lca19-symbiflow

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Synthesis & Mapping & PnR

Synthesis

FPGA Tools

Verification, Testing, �& Simulation

Verilog To Routing

nextpnr

Project�X-Ray

Project�Trellis

Architecture Definitions

Yosys

Project�IceStorm

Both timing driven!

j.mp/lca19-symbiflow

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Synthesis & Mapping & PnR

Project�X-Ray

Project�Trellis

Project�IceStorm

Project�2064

Verilog To Routing

- Basic Blocks

- Advanced Blocks

- Routing

- Bit Gen

nextpnr

- Basic Blocks

- Advanced Blocks

- Routing

- Bit Gen

Yosys

- Basic

- DSP

- Advanced

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nextpnr

Lattice

iCE40

Should beat Arachne-PnR

j.mp/lca19-symbiflow

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nextpnr

Lattice iCE40

Anything!

Just use it!

Should beat Arachne-PnR

(Otherwise a bug!)

j.mp/lca19-symbiflow

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nextpnr

Lattice iCE40

Should beat Arachne-PnR

(Otherwise a bug!)

Use the tools

Report bugs!

You can help!

j.mp/lca19-symbiflow

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nextpnr

Lattice iCE40

Should beat Arachne-PnR

(Otherwise a bug!)

Update yor

tutorials!

You can help!

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j.mp/fomu-cs

j.mp/lca19-symbiflow

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nextpnr

Lattice

ECP5

j.mp/lca19-symbiflow

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nextpnr

Lattice ECP5

IoT "microcontroller" SoC

Linux "microprocessor" SoC

Still early, but

ready for experimenting!

j.mp/lca19-symbiflow

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nextpnr

Lattice ECP5

Use the tools

Report bugs!

You can help!

j.mp/lca19-symbiflow

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Verilog �to �Routing

Lattice

iCE40

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Verilog to Routing

Lattice iCE40

Logic + Block RAM

Simple IOB, No DSP

Blinky

IoT "microcontroller" SoC

Very early, need help!

j.mp/lca19-symbiflow

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Verilog to Routing

Lattice iCE40

Logic + Block RAM

Simple IOB, No DSP

Blinky

IoT "microcontroller" SoC

Very early, need help!

You can help!

j.mp/lca19-symbiflow

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Verilog �to �Routing

Xilinx

Artix 7

Artix-7 “Region of Interest” as �shown in Verilog to Routing

Artix-7 CLBLL_L internals as �shown in Verilog to Routing

j.mp/lca19-symbiflow

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Verilog to Routing

Xilinx Artix 7

Logic + DRAM

Blinky + Counter

RAM tester

Very early, need help!

j.mp/lca19-symbiflow

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Verilog to Routing

Xilinx Artix 7

Logic + DRAM

Blinky + Counter

RAM tester

IoT "microcontroller" SoC

Very early, need help!

You can help!

j.mp/lca19-symbiflow

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Synthesis & Mapping & PnR

Project�X-Ray

Project�Trellis

Project�IceStorm

Project�2064

Verilog To Routing

- Basic Blocks

- Advanced Blocks

- Routing

- Bit Gen

nextpnr

- Basic Blocks

- Advanced Blocks

- Routing

- Bit Gen

Yosys

- Basic

- DSP

- Advanced

More?

You can help!

☑

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How to help?

We need you!

j.mp/lca19-symbiflow

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The more help, the better things get!

You can help!

j.mp/lca19-symbiflow

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All most all scripts are �written in Python

Do you know Python?

You can help!

j.mp/lca19-symbiflow

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Do you know C++?

VPR & nextpnr & libraries�written in C++

You can help!

j.mp/lca19-symbiflow

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Do you know TCL?

All the EDA tools use TCL

You can help!

j.mp/lca19-symbiflow

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Do you know Verilog?

Simulation and models�are written in Verilog

You can help!

j.mp/lca19-symbiflow

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Do you know XML?

Most file formats� are XML

You can help!

j.mp/lca19-symbiflow

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Do you know English?

Documentation is �written in English

You can help!

j.mp/lca19-symbiflow

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Do you know Docker?

Help make it

easier to set up

You can help!

j.mp/lca19-symbiflow

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Do you have time?

I will find you a task

You can help!

j.mp/lca19-symbiflow

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Questions?

I will find you a task

GitHub - https://github.com/symbiflow

Mailing List - https://lists.librecores.org/listinfo/symbiflow

My email - me@mith.ro

j.mp/lca19-symbiflow

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The end!

j.mp/lca19-symbiflow

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I'm Tomu

A microcontroller or FPGA which fits inside your USB port

j.mp/lca19-symbiflow

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j.mp/fomu-cs

j.mp/lca19-symbiflow

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j.mp/fomu-cs

j.mp/lca19-symbiflow

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j.mp/fomu-cs

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j.mp/fomu-cs

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j.mp/fomu-cs

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j.mp/fomu-cs

j.mp/lca19-symbiflow

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The end!

j.mp/lca19-symbiflow

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nextpnr or VPR

j.mp/lca19-symbiflow

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nextpnr or VPR?

Project�X-Ray

Project�Trellis

Project�IceStorm

Verilog To Routing

- Basic Blocks

- Advanced Blocks

- Routing

- Bit Gen

nextpnr

- Basic Blocks

- Advanced Blocks

- Routing

- Bit Gen

Yosys

- Basic

- DSP

- Advanced

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j.mp/lca19-symbiflow

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nextpnr or VPR?

15 year history
Active research

6 month history
Cool GUI
Better bitgen

j.mp/lca19-symbiflow

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More �EDA ecosystem

details!

j.mp/openfpga-diagram

j.mp/lca19-symbiflow

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Components

j.mp/lca19-symbiflow

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j.mp/lca19-symbiflow

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Simulation� & Testing

Implementation

FPGA

ASIC

Yosys

FASM

Verilog to Routing

Simulation� & Testing

Hardware Description

Manufacturing

Bitgen

Formal Verification

Synthesis

Technology�Mapping

Placement

Routing

Placement

Simulation

Applications

Verilog

VHDL

System�Verilog

Chisel

Migen

Matlab

Testing

...

Implementation

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Simulation� & Testing

Implementation

Hardware Description

Applications

j.mp/lca19-symbiflow