The Low Power Programmable Leader

Server Roadmap, DC-SCM and Security Solutions

Prepared for HPC Platform

Agenda

• Lattice Roadmap
• Lattice DC-SCM Solution
• Lattice DC-SCM details
• DC-SCM Video
• DC-SCM Summary

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2

Agenda

• Lattice Roadmap
• Lattice DC-SCM Solution
• Lattice DC-SCM details
• DC-SCM Video
• DC-SCM Summary
• Lattice Security Solutions
• Lattice Supply Guard

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3

Lattice Control and Secure FPGAs

2019

2020

Robustness / Security

2013

Control

2005

Low density non-volatile FPGA leader

Secure

• Affordable Enterprise Security

Flexible/Ease of Use/Reliable

• High IO-to-logic ratio
• Fast Boot, dual/multi-images

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High LC

Secure

Released

Development

4 - LATTICE SEMICONDUCTOR

4

July 2021

Agenda

• Lattice Roadmap
• Lattice DC-SCM Solution
• Lattice DC-SCM details
• DC-SCM Video
• DC-SCM Summary
• Lattice Security Solutions
• Lattice Supply Guard

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5

Server Platform Design Trend

TODAY

Monolithic Server Motherboard

2022

Modular Server Motherboard & DC-SCM

CPU0

CPU1

SPI

SPI

Modular designs are accelerating in 2022

6 | Lattice Semiconductor Confidential

Signal Aggregation on iCE40

We have signal aggregation IP on iCE40 FPGAs

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iCE40 UltraPlus is the world’s smallest FPGAs with enhanced memory & DSPs

• Our sensor data fusion with embedded RISC-V and multi-sensor aggregation demo (https://www.youtube.com/watch?v=xpFFXbtazco)

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• Up to seven channels can be aggregated.
• Raw data rate on Single-Wire is configurable as ~7.5 Mbps or higher.
• Supports I2C at 100 kpps, Fast-Mode (400 kbps) and Fast-Mode Plus (1 Mbps.)
• I2C Interrupt can be realized by GPIO with event-based transmission.
• Multiple sets of ready-to-use configurations to support different use case applications are available.
• The configuration of the device is set through SRAM which provide the flexibility to be reprogram in the field.

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7 - LATTICE SEMICONDUCTOR

7

July 2021

Signal Aggregation Reference Design/Demo for DC-SCM

Implemented spec-compliant, signal aggregated LVDS Link (MCSI)

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• Compliant with DC-SCM Protocol Specifications 2.0
• Aggregates GPIO’s, I2C’s, UARTS, Data and OEM Channels into bi-directional LVDS link
• Scalable to support over 800MHz link
• Supports up to 64-bit GPIO channels, with sampling rate of 90 kHz
• Supports up to 7 channels aggregation/disaggregation in total
• Supports a fixed 400Mbps LVDS data rate

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MachXO3 Reference Design was demonstrated on November 2021, at OCP Global Summit

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Full productized, validated IP released by Mid year 2022

8 - LATTICE SEMICONDUCTOR

8

July 2021

DC-SCM: Closer Look

• Lattice supports LTPI: LVDS Tunneling Protocol & Interface
• This component uses an FPGA to aggregate many GPIO, GPIO, UART, I2C and other signals into a bi-directional LVDS signal.
• Lattice’s scalable solution will support this functionality on both the BMC (SCM) module as well as the motherboard (HPM).
• Larger Lattice devices provide free LUT’s for added functions, such as power sequencing and/or security

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LTPI: LVDS Tunneling Protocol & Interface

9 - LATTICE SEMICONDUCTOR

9

July 2021

DC-SCM Video

DC-SCM Summary�First to Market and Designed to Stay�

Lattice is dedicated to DC-SCM 2.0 rollout

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Lattice will support both SCM and the HPM link solutions.

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Lattice offers a wide range of DC-SCM-compatible solutions. We provide a specification-compliant path to grow to higher performance, higher-featured solutions for years to come

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Customers can also integrate additional functionality, including PFR security and power management, with Lattice Mach-NX and Next Gen FPGAs

11 - LATTICE SEMICONDUCTOR

11

July 2021

Thank You

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12

July 2021