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SERVER

OCP NIC Community Update�September 2025

for Server Project

�����Sub-group Project Wiki: https://www.opencompute.org/wiki/Server/NIC�

Mailing List: https://ocp-all.groups.io/g/OCP-NIC

NIC3.0

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Agenda

  • 2025 OCP Global Summit
  • Thermal Test Fixture update
  • SI workstream PCIe Gen7 kick-off
  • Thermal workstream update
  • NIC form factor workstream update

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OCP Global Summit

  • October 13th - 16th, 2025 - San Jose Convention Center
  • Presentations
    • Scaling OCP NIC to 1.6T and beyond for AI - Oct 15th, 10:05 AM, 220B
    • OCP NIC 2025: Now and Beyond - Oct. 15th, 11:05 AM, 220B
  • Full schedule: https://2025ocpglobal.fnvirtual.app/a/schedule/

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OCP Global Summit

  • Innovation Village Demo
    • Prep led by Spirent/Pio
    • Broadcom, Dell, Intel, Meta, Spirent, Portwell participating in demo

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DSFF Thermal Test Fixture Overview

  • Dell developing a new Thermal Test Fixture (TTF) to support SFF / TSFF / DSFF / TDSFF form factors at PCIe® speeds up to Gen 7
  • PCB designed to extend PCIe lanes from a DC-MHS compatible server to a mounted OCP 3.0 DUT card
  • Metal housing intended to attach to a wind tunnel or flow bench
  • Each form factor will leverage a different front bracket
  • Pre-defined sensor locations for test repeatability
  • Onboard MCU operates like prior thermal test fixtures and codebase to be contributed to the OCP GitHub repository
  • Update: Next rev PCB protos to arrive before OCP Summit
    • Next steps
      • TDSFF, TSFF, SFF brackets built
      • Thermal testing underway

DSFF Thermal Test Fixture

DSFF TTF Airflow Operation

Please note: PCIE® design mark is a registered

trademark and/or service mark of PCI-SIG.

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Signal Integrity / Fixture updates

  • OCP NIC 3.0 suppliers shall follow PCIe® routing specifications
  • Section 5.3.2 defines test fixtures used for compliance testing
    • Compliance Load Board (CLB) – test systems with OCP NIC 3.0 slots
    • Compliance Base Board (CBB) – test OCP NIC 3.0 mezzanine cards
  • OCP NIC 3.0 CLB & CBB test fixtures designed to:
    • Emulate the PCIe’s CEM CLB & CBB fixtures
    • Leverage PCIe test equipment automation without significant modification
  • The OCP-NIC sub-group recently chartered an SI workstream to contribute Gen 7 conformance / informative limits in adherence to the the PCI SIG’s policies
  • These SI limits and their associated SI fixtures to be contributed in the OCP NIC v1.7 spec, which is targeted to release before the end of the year

Please note: PCIE® design mark is a registered

trademark and/or service mark of PCI-SIG.

Compliance Base Board

Compliance Load Board

Next SI workstream mtg Sept 25th

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Thermal Workstream Update

  • TSFF, DSFF/TDSFF thermal spec updates
    • TSFF spec updates complete
    • DSFF/TDSFF is in progress
      • Detailed thermal model
      • Design guidance plots
    • Spec update review targeted for end of September/early October

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  • Liquid Cooling Feasibility Study Ongoing
    • Thermally this option offers lots of capability
    • Detailed mechanical feasibility studies in progress
      • TSFF is target of study

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Form-factor workstream: What are we try to solve for?

  • Higher density & higher bandwidth NIC solution than PMM & DSFF offering today

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  • Bifurcation of x32 solutions that hard to converge

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Existing NIC form-factor ecosystems

Long-side attachment

PCIe CEM

APEC

HyperScale #1 FF

Short-side attachment

OCP NIC (T)SFF

PMM

HyperScale #2 FF

Vendor #1 FF

x16

x16

x32

x32

x32

x32

x32

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Proposed x64 Concept

  • Up to x64. Support x32.
  • Up to PCIe Gen7
  • 2x OSFP concept study
  • Up to 600W @ 12v
  • Support BE-NIC use-case with additional x8/x4 to CPU
  • Expect liquid cooling
  • No hot-swap support

167mm

107.1mm

PLACEHOLDER

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Thank You

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PMM Analysis Summary

  • Overall: larger cooling envelope, better width for 32 lanes

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  • PMM similar to the OCP NIC DSFF (& LFF), yet different
    • Pros: 600W, SGMII, smaller chassis width for 32 lanes, tall bracket (room for cooling options)
    • Cons: Multiple form-factor depths & bracket options, not compatible to DC-MHS
  • Other cons:
    • Larger depth impacts HPMs
    • Board thickness limited to 1.6mm, limits high number of host PCIe and media signal routing required for >1 Tbps adapters
    • No public market traction with PMM, no ongoing SNIA activity

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PMM form factors

167 mm long x 120 mm wide x 18.30 mm

167 mm long x 120 mm wide x 38.40 mm

230 mm long x 120 mm wide x 18.30 mm

230 mm long x 120 mm wide x 38.40 mm

TA-1037

TA-1002

Compatible

PWR

Lanes 17-32

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Leveraging PMM advantages to iterate OCP NIC 3.0

  • Is PMM power attractive? Add TA-1002 Type 2 connectors for SFF / DSFF

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  • Is PMM chassis width better than DSFF? Revive legacy LFF (+ Type 2)

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  • Is PMM taller bracket necessary? Intel’s 1U OCP NIC bracket proposal

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