Advanced Packaging for AI/HPC

September 10, 2026

Charles Woychik

cwoychik@nhanced-semi.com

630-561-6813

Recent Announcements

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Photonics Advantage

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3

As the demand for faster and more efficient data processing grows,

photonics will be a critical component of future technological advancements

© Quantum Computing Inc.

All At Room Temperature

Photonics enables the mass production of quantum hardware by adapting standard semiconductor foundry processes

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Our Story & Recognition

NHanced Background

• We target specialty niche markets with Advanced Packaging,

Additive Manufacturing, and specialty BEoL:

• Photonics
• Fluidics
• True Heterogenous Integration
• RadHard
• Quantum devices
• FPGAs
• Memory including ReRAM, MRAM, FeRAM, EEPROM, DRAM, SRAM
• AI/ML/Exascale
• RFID
• Medical
• Down-hole to deep-cryo
• Mixed Commercial and A&D customers
• Development and production

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Batavia IL, Headquarters

Design engineering,

Test, board level work, and back office.

Morrisville NC, Fab 1

Prototyping, pilot line, and LV manufacturing

~7k sq. ft. Fab area

>100 tools

Manual tools – high customization

Odon IN, Fab 2

“HVM” manufacturing

~7k sq. ft. Fab area

Automated/Semiautomated tools – high throughput, CPK monitor controlled

Specialized Materials:

• Interposers: silicon, glass, and fused silica
• Optical and electrical interconnect
• Advanced substrates: silicon, GaN, GaAs, InP, GaSb, LiNbO3, BTO, SiC, TFLN, etc.

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AP Assembly:

• Flip-chip
• Solder ball drop
• Co-packaged optics
• Interposer and substrate

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Advanced Packaging:

• HDI edge packaging
• Chiplet integration
• TSV insertion
• Covalent oxide bonding
• Hybrid copper and nickel bonding
• True heterogeneous integration
• Transfer printing assembly
• Wafer reconstitution
• Die-to-die, die-to-wafer, and wafer-to-wafer 2.5D and 3D integration

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NHanced Standard Capabilities

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Key Tools and Capabilities

• Die2Wafer & Wafer2Wafer Bonding
• BESI Next Gen
• Better than 200nm accuracy
• >2k die per hour
• >three 9s going to five 9s
• Laurie
• Bosch Etch
• PlasmaTherm
• Oxide/Nitride
• Trion
• Low temperature – down to 70C oxides
• Stress balanced
• P5000
• Pd/Au Plating
• Quantum device enablement
• UBM
• Large TSV Fill
• 50x300um, 25x200um

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• Oxide Etch
• AMAT P5000s
• PVD
• Endura 5500
• Metrology
• Next gen ultrasound
• X-ray
• CDSEM
• Production Plater
• Raider
• Solder Plating
• Lead Free
• Solder Ball Drop
• Lead Free
• Leaded
• In
• Bi/X
• RIE Metal Etch
• Oxford

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• I-Line Litho
• NXQ8000
• Full wafer reticle – stitchless interposers to full wafer size
• Near I-line stepper performance: 1um L/S
• Through wafer IR alignment
• Ultra-Tech Saturns
• ALD
• High aspect ratio TSV barrier and seed
• High k thin films
• Extensive CMP
• Oxide, Silicon, Barrier, Cu, Ni, Ru
• Wafer Grinding

NHanced Small/Medium Scale � – High Touch Manufacturing

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• 2.5/3D Advanced Packaging
• Si Sensors
• Commercial Development
• Mil-Aero Development and Manufacturing
• Full BEoL
• Niche BEoL Processes
• Cu, Ni, Al, +
• Split-Fab
• High k-caps
• ReRAM
• 3/5 and LiNbO3 integration
• Thick Wafer & Thin Wafer Processing
• ISO9001

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• Target market is customers needing

1 to 5000 wafers per year

NHanced High Volume Manufacturing� – Customized At-Scale Manufacturing

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• 2.5/3D Advanced Packaging
• Hybrid Bonding
• Customize Metal Stack
• Interposers
• Silicon
• Glass
• Target market is customers needing

500 to 50,000 wafers per year

NHanced Market Messaging

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It’s All About The Wire

• Wire length controls the delay
• Span of control
• Accounts for majority of power usage
• Memory fetch is an extreme example

By the mid 90’s wire was already becoming the dominant delay limiting performance. The GaAs FPGA demonstrated this perfectly. The transistor performance improvement of GaAs didn’t matter for the FPGA. It was the wire.

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3DInCities

Effective End of Moore’s Law

Moore’s Law was first and foremost a statement about economics. We could shrink transistors and build more of them for about the same cost.

• This has been the basic premise of the semiconductor industry for 50 years and was true up until the last few years.
• Today we can indeed shrink transistors further, but the cost per transistor no longer declines.

We can get something a little more compact

• Perhaps a little less power
• But we pay more for these features now.

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Intel

2¹⁰ Scaling in 40 years

2µm → 2nm

One can see the atoms with this 6nm device. It is obvious we can’t scale much more.

Maybe to 1nm?

Moore’s Law Is About Cost

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Chip Design and Manufacturing Cost under Different Process Nodes: Data Source from IBS

EETimes

Single pattern 193i lithography reaches its limit.

Smaller nodes required double patterning and/or EUV.

Lithography already the single most expensive step in semiconductor manufacturing doubles or triples in cost after the 28nm node – effectively ending Moore’s Law.

Runaway Development Costs

Performance Limited by Wire

Foundry 1.0: The Industry Today

• Current semiconductor business has been focused on driving smaller transistors.
• This is a safe path with 50 years of historic success!
• But…
• High development cost
• High capital cost
• Long development times
• Expensive design tools
• High risk
• It is the Twilight of Moore’s Law

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TSMC

What Does This Mean?

The semiconductor industry is about to undergo a sea change.

• New ways of accomplishing Moore’s law economics and performance are needed.
• The industry is now looking to use advanced packaging to drive future semiconductors.
• Better Cost
• Better Performance
• Better SWaP

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The revolution in semiconductors is reminiscent of the revolution in locomotives. The locomotive builders reached a tipping point driven by cost. After which, diesels which had been around for 20 years, almost over night replaced steam locomotives. The steam engine incremental improvements no longer were ample to sustain the industry.

The economics drove the change.

Foundry 2.0 –

A Finishing Foundry that takes the standardized building blocks from traditional semiconductor manufacturers and uses advanced packaging and additive manufacturing to create highly customized components with superior performance targeting small and medium sized markets.

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A New Semiconductor Industry Paradigm

Foundry 2.0

• System solution focus
• Best of class components
• Relies on Advanced Packaging (AP) and Chiplets
• Heterogenous integration
• Photonics
• MEMS
• RF
• Advantages
• Low development cost
• Low capital cost
• Short development times
• Inexpensive design tools
• Low risk

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3DinCites

Philips

EETimes/Intel

Honeywell

AP Drivers: AI, Quantum, & Integrated Sensors

• Advanced Packaging I/O
• Tb/s, <<100fJ/b
• SiP 500ff I/O Load
• 2.5D 25ff I/O Load
• 3D 3ff I/O Load
• AI Musts:
• Local Memory
• >100TB/s

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Intel

Tyndall National Institute Carroll et al

Nature 29 January 2021 Shastri

Honeywell

AP Drivers: Internet Of Things

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The IoT requires sensors, processors, RF, energy harvesting, and often special materials to meet the industry needs.

More Than Moore

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GEORGIA TECH PRC

These new technologies and IoT are requiring introduction of new materials and processes that are often incompatible with CMOS. Advanced Packaging provides a mechanism for the tightly coupled integration of these new elements into true complete systems in a package with often far superior performance and lower power.

Hybrid Bonding – A Keystone Technology

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The Enabler for Next Generation Advanced Packaging.

DBI^®: Low Temperature Hybrid Bonding Process

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Jihoon Seo / Materials Research Society

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1.9 µm DBI^® pitch, 300℃

1.6 µm DBI^® pitch, 300℃

Scalable To < 1um Pitch

0.8um Pitch Demonstrated

Cu/SiO DBI^® Hybrid Bonding

Hybrid Bonding Interconnect Pitch Scaling

• WtoW 3sigma < ±1um misalign performance
• DtoW 3sigma < ±100nm misalign performance
• Production Minimum pitch = 2um

P=3.2um

0.3um

Driving Die-to-Wafer Progress

• The BESI Datacon 8800 CHAMEO ultra plus AC D2W bonding system that can reach >200nm of accuracy for each bond.
• To reach this level of accuracy the tool has demanding requirements that need to be fulfilled like:
• Advanced tooling for the tool
• Time and Cost
• Plasma singulation needed
• Specific types of key patterning and placement
• Clear field
• DRC waivers
• Fiducial material design
• Contrast
• Film frame picking

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AP Cornerstones: Embedded 2.5/3D ─ Wafer Reconstitution

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ASE

HRL

DECA Technologies

Wafer reconstruction and adaptative substrates provide additional flexibility and next level packaging alternatives.

AP Cornerstones: Chiplets

• Provides:
• Best of Class Everything
• Easy retargeting
• Lower risk
• IP reuse
• Lower cost

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Intel

Intel

AMD

nVidia

Z-Glue

AP Cornerstones: Interposers

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• Up to full wafer scale interposers
• HP 2um thick wiring is standard
• 4um, 6um, 10um, layer options
• Embedded decoupling caps and 12 wiring layers coming
• Optical waveguides

Mosaic Microsystems

AP Extensions: Cooling, Microfluidics and Diamonds

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Chip Scale Cooling

For Ultra-Dense AI Electronics

AP Extensions: Micro-Connections and 3D Structures

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(top left) Quilt Packaging concept cross-section illustration & image of a post-reflowed QP CMOS quilt; (bottom left) SEM image of quilted chip-to-chip seam of >10 micron width; (top right) QP-enabled miniature curved array demonstration article; (bottom right) profile view of QP-enabled miniature curved array.

IIC

Bacteria-World

techunwrapped.com

MEMS + Precision Interconnects

Why Are We Headed To Low/Medium Volume Manufacturing?

• Transistor cost is increasing
• To reduce cost, we need to sell the consumer fewer transistors
• Most semiconductor devices have the kitchen sink
• NRE is high so we can’t target markets
• Chiplets offer reuse – effectively $0 NRE
• Advanced packaging NREs run ~100x less cost than lead edge node NREs
• Chiplet to chiplet power and delay is competitive with on die
• Chiplets can target markets – use only necessary transistors

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→ Low NRE → Niche Market → Fewer Transistors → Lower Cost Composite Device

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Moore’s Law for the Next Decade

A Change In Perspective Foundry 2.0

• A new focus on next generation semiconductors created by
• Advanced Packaging
• Additive Semiconductor Manufacturing
• True heterogenous integration
• Interconnect focused – all BEoL additive
• Better ROI
• Lower development costs
• Lower CAPEX
• Leveraging existing foundries
• Split Fab
• More Than Moore Technologies
• IP Centric
• IP driven value – not cost of capital

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System Level Moore’s Law

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Split Rock Lens – StackExchange