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Mantra�Qubit Movement-Optimized Program Generation�on Zoned Neutral Atom Processors�

Enhyeok Jang (Yonsei University), Youngmin Kim (Yonsei University), Hyungseok Kim (Yonsei University), �Seungwoo Choi (Yonsei University), Yipeng Huang (Rutgers University), and Won Woo Ro (Yonsei University)

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E-mail: {enhyeok.jang, wro}@yonsei.ac.kr, yipeng.haung@rutgers.edu��Proceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization,

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March 1-5, 2025, Las Vegas, NV, USA

�Session: Quantum Computing (2) at Room Willow, 11:40 – 12:00

Tuesday, Mar 4th, 2025

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Contents

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  • Background and Motivation
  • Mantra Design
  • Experimental Methodology
  • Results and Analyses
  • Conclusion

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Contents

​

  • Background and Motivation
  • Mantra Design
  • Experimental Methodology
  • Results and Analyses
  • Conclusion

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[Target Architecture]

  • Zoned Architecture [1] (Isolating Gate Area)
    • Long coherence times (~100s)
    • High Reconfigurability

​

​

4

[1] Dolev Bluvstein et al. "Logical quantum processor based on reconfigurable atom arrays." Nature 626.7997 (2024): 58-65.

< Zoned Architecture >

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[Target Architecture]

  • Zoned Architecture [1] (Isolating Gate Area)
    • Long coherence times (~100s)
    • High Reconfigurability

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[Potential Concerns]

  • 1Q and 2Q gates are interleaved frequently
    • Inter-zone movements of atoms !
  • Trap speed of neutral atom: 0.55 m/s (for trapped ions: 10 - 30 m/s)

​

​

5

[1] Dolev Bluvstein et al. "Logical quantum processor based on reconfigurable atom arrays." Nature 626.7997 (2024): 58-65.

< Zoned Architecture >

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[Target Architecture]

  • Zoned Architecture [1] (Isolating Gate Area)
    • Long coherence times (~100s)
    • High Reconfigurability

​

[Potential Concerns]

  • 1Q and 2Q gates are interleaved frequently
    • Inter-zone movements of atoms !
  • Trap speed of neutral atom: 0.55 m/s (for trapped ions: 10 - 30 m/s)
  • Inter-zone travel overhead: Average of 78%, Up to 89%

​

​

6

[1] Dolev Bluvstein et al. "Logical quantum processor based on reconfigurable atom arrays." Nature 626.7997 (2024): 58-65.

< Zoned Architecture >

< Runtime Breakdown on Zoned Arch. >

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[Target Architecture]

  • Zoned Architecture [1] (Isolating Gate Area)
    • Long coherence times (~100s)
    • High Reconfigurability

​

[Potential Concerns]

  • 1Q and 2Q gates are interleaved frequently
    • Inter-zone movements of atoms !
  • Trap speed of neutral atom: 0.55 m/s (for trapped ions: 10 - 30 m/s)
  • Inter-zone travel overhead: Average of 78%, Up to 89%

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[Focus]

  • Reducing Inter-zone movements of atoms

7

[1] Dolev Bluvstein et al. "Logical quantum processor based on reconfigurable atom arrays." Nature 626.7997 (2024): 58-65.

< Zoned Architecture >

< Runtime Breakdown on Zoned Arch. >

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[Atom movement is not completely free.]

8

1L

0L

1L

0L

1L

0L

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[Let us SWAP 2 Logical Qubits in Moving Traps …]

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9

1L

0L

0L

1L

0L

1L

1L

0L

1L

0L

1L

0L

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[Let us SWAP 2 Logical Qubits in Moving Traps …]

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10

1L

0L

0L

1L

0L

1L

1L

0L

150 us

1L

0L

(40 um)

/�(. 55 m/s)

=

72.8 us

150 us

(20 um)

/�(. 55 m/s)

=

36.4 us

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[Atom movement is not completely free.]

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  • Moving Traps cannot cross [2] each other.
  • Transversal CZ is realized between 2 atoms in very close.
    • One of atoms is in a moving trap (AOD) �and the other in a static trap (SLM) [3].
  • Atom transfer time between AOD and SLM takes long: 150 us�(~ hundreds times of 2Q gate pulse, 380 ns) [4].

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[2] Chen Huang et al. "ZAP: Zoned Architecture and Parallelizable Compiler for Field Programmable Atom Array." arXiv preprint arXiv:2411.14037 (2024).�[3] Wan-Hsuan Lin, Daniel Bochen Tan, and Jason Cong. "Reuse-aware compilation for zoned quantum architectures based on neutral atoms." arXiv preprint arXiv:2411.11784 (2024).

[4] Jixuan Ruan et al. "PowerMove: Optimizing Compilation for Neutral Atom Quantum Computers with Zoned Architecture." arXiv preprint arXiv:2411.12263 (2024).

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[Atom movement is not completely free.]

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  • Moving Traps cannot cross [2] each other.
  • Transversal CZ is realized between 2 atoms in very close.
    • One of atoms is in a moving trap (AOD) �and the other in a static trap (SLM) [3].
  • Atom transfer time between AOD and SLM takes long: 150 us�(~ hundreds times of 2Q gate pulse, 380 ns) [4].

​

[These constraints may be difficult to address sufficiently by low-level compilation alone.]

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=> Rewrite quantum programs to make these constraints less happened in the first place.

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[2] Chen Huang et al. "ZAP: Zoned Architecture and Parallelizable Compiler for Field Programmable Atom Array." arXiv preprint arXiv:2411.14037 (2024).�[3] Wan-Hsuan Lin, Daniel Bochen Tan, and Jason Cong. "Reuse-aware compilation for zoned quantum architectures based on neutral atoms." arXiv preprint arXiv:2411.11784 (2024).

[4] Jixuan Ruan et al. "PowerMove: Optimizing Compilation for Neutral Atom Quantum Computers with Zoned Architecture." arXiv preprint arXiv:2411.12263 (2024).

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Contents

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  • Background and Motivation
  • Mantra Design
  • Experimental Methodology
  • Results and Analyses
  • Conclusion

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[Rewriting Motivations and Designs]

  • Exploiting high flexibility of unitary decomposition�(e.g., fermionic system simulation kernels).

V-chain

  • has been typically adopted for super-conducting qubits.
  • has frequent interleaving of 1Q and 2Q gates in CZ-based decomposition.

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=> requires frequent inter-zone movement when running on ZA. ☹

​

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Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

< Existing Simulation Kernel and Its Translation >

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[Rewriting Motivations and Designs]

  • Exploiting high flexibility of unitary decomposition�(e.g., fermionic system simulation kernels).

Rewrite them as Fountain-chain

  • Hadamard is self-adjoint.
  • Applying them in even numbers => Identity Operation
  • Gate cancellation => Interleaving between CZs is resolved
  • Only one qubit (0L) is moved to compute all CZs.
  • No trap transfer required.

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  • Cleverly decompose the Hamiltonian so that�inter-zone movements would not be frequent �from the begining ☺.

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Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

< Existing Simulation Kernel and Its Translation >

< Proposed Simulation Kernel and Its Translation >

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[Inter-Zone Movement Complexity]

V-chain

  • 4 * ((# of Qubits) – 1) * (# of Paulis)

Fountain-chain

  • 4 * 4 * (# of Paulis)

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Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

< Proposed Simulation Kernel and Its Translation >

< Existing Simulation Kernel and Its Translation >

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[Rewriting Motivations and Designs]

  • Exploiting native Rydberg gates
  • A bunch of RZZs
    • Cost Hamiltonian in QAOA
    • QNN Ansatz

​

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Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

< Existing Simulation Kernel and Its Translation >

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[Rewriting Motivations and Designs]

  • Exploiting native Rydberg gates
  • A bunch of RZZs
    • Cost Hamiltonian in QAOA
    • QNN Ansatz
    • New Gate Protocol

​

18

Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

< Existing Simulation Kernel and Its Translation >

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[Inter-Zone Movement Complexity]

CX-Based RZZ Decomp.

  • 2-Local: 8 * (# of QAOA Layers)
  • SK: 4 * (# of Qubits) * (# of QAOA Layers)

Proposed Protocol

  • 2 * (# of QAOA Layers), No Trap Transfer

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Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

< Existing Simulation Kernel and Its Translation >

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[Rewriting Motivations and Designs]

  • Intentionally execute some gates earlier/later
  • Basic Principle: �Greedy execution of all gates that can be�processed in the Zone currently located.
  • Gates has computational dependency�with each other.

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=> Executing as many gates as possible �at each moment can ensure optimal �execution globally as well.

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Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

< Applying Gate Sched. on GHZ w/ Parallel CXs >

< Applying Gate Sched. on GHZ w/ Fountain CXs >

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Contents

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  • Background and Motivation
  • Mantra Design
  • Experimental Methodology
  • Results and Analyses
  • Conclusion

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Modeling Zoned Architecture

    • Hardware Parameters from ZA [1]

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    • Additional Execution Policies
      • Transferring Traps in Advance:�While Q_a is coming from the storage zone, �Q_b is pre-transferred to the SLM trap.
      • Placing Qubits near Zone Borders

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    • Program Run Scenarios
      • Standard (No Opt.)
      • NALAC [4]
      • Mantra (Proposed)�

​

​

22

[1] Dolev Bluvstein et al. "Logical quantum processor based on reconfigurable atom arrays." Nature 626.7997 (2024): 58-65.

[4] Yannick Stade et al. 2024. “An Abstract Model and Efficient Routing for Logical Entangling Gates on Zoned Neutral Atom Architectures.” arXiv preprint arXiv:2405.08068 (2024).

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Contents

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  • Background and Motivation
  • Mantra Design
  • Experimental Methodology
  • Results and Analyses
  • Conclusion

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Molecular Simulation Circuits (UCCSD Ansatz)

    • Perf. of NALAC over Standard: 36% (Total Runtime), 33% (LD/ST Time)
    • Perf. of Mantra over Standard: 79% (Total Runtime), 86% (LD/ST Time)
    • LD/ST Time Ratio in Total Runtime
      • Standard (92%), NALAC (96%), Mantra (61%)

24

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Molecular Simulation Circuits (UCCSD Ansatz)

    • Perf. of NALAC over Standard: 36% (Total Runtime), 33% (LD/ST Time)
    • Perf. of Mantra over Standard: 79% (Total Runtime), 86% (LD/ST Time)
    • LD/ST Time Ratio in Total Runtime
      • Standard (92%), NALAC (96%), Mantra (61%)
    • Mantra: Constant LD/ST per Pauli-String regardless of molecules.

25

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QAOA Circuits (Maximum Cut Problem)

    • PL: Perf. of Mantra over NALAC: average of 79% (62%-89%)
      • Runtime Scalabilty by # of Qubits: Nearly direct
      • Runtime Scalabilty by # of QAOA Layers: Direct
    • SK: Perf. of Mantra over NALAC: average of 86% (75%-91%)
      • Runtime Scalabilty by # of Qubits: Nearly quadratic
      • Runtime Scalabilty by # of QAOA Layers: Direct

26

Power-Law

Graph

SK-model

Graph

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Contents

​

  • Background and Motivation
  • Mantra Design
  • Experimental Methodology
  • Results and Analyses
  • Conclusion

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Conclusion

    • ZA is an emerging architecture that realizes high-precision quantum computing.

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    • If existing program structures are applied naively to ZA, �most of the execution may be devoted to traveling between zones.

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    • Existing CX-based representations for static topologies can cause frequently gate-interleaving on ZA.

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    • To reduce 1Q/2Q gate interleaving, we propose Mantra.
      • Fountain-Shaped Tree Chain => Good for Inter-Zone Moves, Trap Transfer
      • ZZ-Interaction Protocol w/o 1Q Gate => Exploiting Native Ops of ZA
      • Preemptive Identical-Zoned Gate Sched. => Greedy Run for Same-Zone Gates

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    • w/o hardware modifications, Mantra reduces �inter-zone moves by 68%, # of gates by 35%, and improves fidelity by 17%

​

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Mantra Contributors

Enhyeok Jang

Seungwoo Choi

Youngmin Kim

Hyungseok Kim

Prof. Yipeng Huang

Prof. Won Woo Ro

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​

​

Thank You for Your Time!��Q & A

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Supplementary

    • Logical Qubit Preparation

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Gate-Based SWAP in ZA

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[Previous Neutral Atom Compilers]

=> Not effective enough for zoned architectures.

​

  • Exploiting long-distance entangling [5]: �But, ZA adopt Transversal CZ.
  • Reducing intra-zone movements efficiently ☺ [6]:�But, designed not for reducing inter-zone movements ☹
  • Designing for ZA [7]:�But, could not reduce inter-zone movements

​

33

[5] Jonathan Baker et al. 2021. “Exploiting longdistance interactions and tolerating atom loss in neutral atom quantum architectures.” In 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 818–831.

[6] Hanrui Wang et al. 2024. “Atomique: A quantum compiler for reconfigurable neutral atom arrays.” In 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA). IEEE, 293–309.

[7] Yannick Stade et al. 2024. “An Abstract Model and Efficient Routing for Logical Entangling Gates on Zoned Neutral Atom Architectures.” arXiv preprint arXiv:2405.08068 (2024).

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[Previous Neutral Atom Compilers]

=> Not effective enough for zoned architectures.

​

  • Exploiting long-distance entangling [5]: �But, ZA adopt Transversal CZ.
  • Reducing intra-zone movements efficiently ☺ [6]:�But, designed not for reducing inter-zone movements ☹
  • Designing for ZA [7]: �But, could not reduce inter-zone movements

=> Existing compilations optimize movements in zones,�But do not reduce movement between zones.

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Need different optimizations than before.

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[5] Jonathan Baker et al. 2021. “Exploiting longdistance interactions and tolerating atom loss in neutral atom quantum architectures.” In 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 818–831.

[6] Hanrui Wang et al. 2024. “Atomique: A quantum compiler for reconfigurable neutral atom arrays.” In 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA). IEEE, 293–309.

[7] Yannick Stade et al. 2024. “An Abstract Model and Efficient Routing for Logical Entangling Gates on Zoned Neutral Atom Architectures.” arXiv preprint arXiv:2405.08068 (2024).

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[Which GHZ Structure is good for ZA?]

GHZ w/ Fountain CXs

  • Depth Complexity: (Q + 1) ☹
  • LD/ST Complexity: 2 ☺

GHZ w/ Parallel CXs

  • Depth Complexity: Log(Q) ☺
  • LD/ST Complexity: ~ Log(Q) ☹

​

35

Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

Entangling

Zone

Storage

Zone

LD

ST

Entangling Zone

Storage Zone

LD

ST

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[Hardware Design Considerations]

Square Array

  • Good flexibility of intra-zone movements ☺
  • Ld/ST overhead is hard to scalable. ☹

​

36

Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

LD

ST

Efficient Design & Placement of Zones

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[Hardware Design Considerations]

Square Array

  • Good flexibility of intra-zone movements ☺
  • Ld/ST overhead is hard to scalable. ☹

Thin-Rectangular Array

  • Low flexibility of intra-zone movements ☹
  • Ld/ST overhead is constant. ☺

​

37

Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

LD

ST

Efficient Design & Placement of Zones

LD

ST

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[Hardware Design Considerations]

Square Array

  • Good flexibility of intra-zone movements ☺
  • Ld/ST overhead is hard to scalable. ☹

Thin-Rectangular Array

  • Low flexibility of intra-zone movements ☹
  • Ld/ST overhead is constant. ☺

3D-Stacked Square Array

  • Good flexibility of intra-zone movements ☺
  • Ld/ST overhead is constant. ☺

​

​

38

Fountain-Shaped�CZ-Tree Chain

ZZ-Interaction Protocol w/o 1Q Gate

Preemptive Identical-Zoned Gate Sched.

Efficient Design & Placement of Zones

LD

ST

LD

ST

LD

ST