Instruction Set Architecture

� �

Recommended: See Links on Class Wiki�

Thanks to Mark Clement of

Brigham Young University for

most of this content.

Learning Objectives…

Learning Outcomes

After completing this section, you should be able to

• Explain what is a computer architecture.
• Describe the differences between a Harvard and von Neumann machine.
• Describe the differences between a RISC and CISC machine.
• Explain the addressing modes of the MSP430.
• Discuss computer instruction cycles.
• Disassemble MSP430 instructions.

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Topics

• ISA
• Von Neumann vs. Harvard
• RISC vs.CISC
• Computer Instructions
• MSP430 ISA
• MSP430 Registers
• MSP430 ALU
• Assembler Primer
• MSP430 Instructions
• Double Operand
• Single Operand
• Jump
• Addressing Modes
• Instruction Length
• Clock Cycles
• Instruction Disassembly

Instruction Set Architecture

• What is an Instruction Set Architecture (ISA)?
• Where the processor stores or obtains information
• Memory organization
• address space -- how may locations can be addressed?
• addressibility -- how many bits per location?
• Register set - how many? what size? how are they used?
• Input / Output devices
• How the processor manipulates data
• Assembly language Instruction set – opcodes, data types, addressing modes
• Processor hardware actions – flow, faults
• The computer ISA defines all the programmer-visible components and operations of the computer.
• ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language).

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ISA

Harvard Architecture

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Von Neumann vs. Harvard

• The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data.

Examples:

8051

Atmel AVR

ARM

The Von Neumann Computer

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MEMORY

Von Neumann�proposed this model in 1946

The Von Neumann model:�Program instructions and Data are both stored as sequences�of bits in computer memory

Von Neumann vs. Harvard

Examples:

Cray

PC’s

MSP430

RISC / CISC Architecture

• Single-clock
• Reduced instructions
• No microcode
• Data explicitly accessed
• Easier to validate
• Larger code sizes (~30%)
• Low cycles/second
• More transistors on memory registers
• Pipelining friendly
• Emphasis on software

• Multi-clock
• Complex instructions
• Complicated microcode
• Memory to memory operations
• Difficult to validate
• Smaller code sizes
• High cycles/second
• More transistors for complex instructions
• Compiler friendly
• Emphasis on hardware

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CISC

RISC

RISC vs. CISC

RISC/CISC Instruction Set

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27 Instructions

RISC vs. CISC

MSP430 Architecture

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Von Neumann

Von Neumann

Bottleneck

Computer Instructions

Computer Instructions

• Computer program consists of a sequence of instructions
• instruction = verb + operand(s)
• stored in memory as 1’s and 0’s
• called machine code.
• Instructions are fetched from memory
• The program counter (PC) holds the memory address of the next instruction (or operand).
• The instruction is stored internal to the CPU in the instruction register (IR).
• Programs execute sequentially through memory
• Execution order is altered by changing the Program Counter.
• A computer clock controls the speed and phases of instruction execution.

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Computer Instructions

Machine vs Assembly Code

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Computer Instructions

Anatomy of Machine Instruction

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“Add the value in Register 4 to the value in Register 5”

Computer Instructions

0101010000000101

How many

instructions are

possible with a

4-bit op-code?

How many

source/destination

registers can

selected with a

4-bit field?

Instruction Addressing Modes

• Machine language instructions operate (verb) on operands (objects).
• Addressing modes define how the computer identifies the operand (or operands) of each instruction.
• Mode encoded within the instruction.
• Determine the size of the instruction.
• Operands are found in
• registers,
• instructions, or
• memory.
• directly,
• indirectly (pointer), or
• indexed.

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Computer Instructions

MSP430 ISA

MSP430 Bus Architecture

• Memory Data Bus (bi-directional)
• Addressability = # of bits stored in each memory location (8-bits).
• Words are always addressed at an even address (little endian).

​

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15

• Memory Address Bus (uni-directional)
• Address Space = number of possible

memory locations (memory size)

MSP430 ISA

• 16-bit ALU (Arithmetic and Logic Unit)
• Sets condition codes: Z, C, N, V
• The master clock (MCLK) drives the CPU and ALU logic.

​

MSP430 Memory Architecture

• Input / Output
• Get information in and out of the computer.
• External devices attached to a computer are called peripherals.
• Lower 512 bytes (0x0000 - 0x01FF) of address space
• 16-bit peripherals (0x0100 - 0x01FF)
• 8-bit peripherals (0x0010 - 0x00FF)
• Special Function Registers – Lower 16 bytes

​

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• Memory
• 64k byte addressable, address space

(0x0000 - 0xFFFF) for most MSP430 (not F5529)

• Flash / ROM – Used for both code/data
• Interrupt vectors - Upper 16 words
• RAM (0x200 - 0x9FF) – Volatile storage

Flash (ROM)

RAM

I/O

0x0000

0xFFFF

MSP430 ISA

MSP430 Ports

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• Computer communicates with external world thru 8 bit memory locations called Ports.
• Each Port bit is independently programmable for Input or Output.
• Edge-selectable input interrupt capability (P1/P2 only) and programmable pull-up/pull-down resistors available.
• Port Registers
• PxIN – read from port
• PxOUT – write to port
• PxDir – set port direction (input or output)

​

​

MSP430 Ports

Quiz 3.1

1. What is an ISA?

​

2. What is a memory address space?

​

3. What is memory addressability?

​

4. What is a computer port?

​

5. List some distinctive properties of the MSP430 ISA.

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Assembly Primer

MSP430 Assembler

• A typical assembly language line has four parts:

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Assembler Primer

• Label — starts in the column 1 and may be followed by a colon (:) for clarity (case sensitive).
• Operation — either an instruction, which is translated into binary machine code or an assembler directive, which controls the assembler (case insensitive).
• Operands — data needed for this operation (not always required).
• Comment — text following a semicolon (;).

Assembler Coding Style

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Assembler Primer

; blinky.asm: Software Toggle P1.0

;*************************************************************

.cdecls C,"msp430.h" ; MSP430 C header

​

DELAY .equ 0

​

.bss cnt,2 ; counter variable

​

.text ; begin code

reset: mov.w #0x0280,SP ; init stack ptr

mov.w #WDTPW+WDTHOLD,&WDTCTL ; stop WDT

bis.b #0x01,&P1DIR ; set P1.0 as output

​

mainloop: xor.b #0x01,&P1OUT ; toggle P1.0

mov.w #DELAY,cnt ; delay counter

​

delayloop: sub.w #1,cnt ; delay over?

jnz delayloop ; n

jmp mainloop ; y, repeat

​

.sect ".reset" ; RESET vector

.word reset ; start address

.end

MSP430 Instructions

MSP430 Instructions

​

• The MSP430 ISA defines 27 instructions with three instruction formats: double operand, single operand, and jumps.
• Single and double operand instructions process word (16-bits) or byte (8-bit) data operations. (Default is word)
• Orthogonal instruction set – every instruction is usable with every addressing mode throughout the entire memory map.
• Includes high register count, no paging, stack processing, memory to memory operations, constant generator.

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Instruction Formats

MSP430 Instructions

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Instruction Register

Program Counter

MSP430 Instructions

R0

1 cycle needed to

fetch instruction

MPS430 Instruction Formats

• Format I: Instructions with two operands:

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MSP430 Instructions

• Format II: Instruction with one operand:

• Format III: Jump instructions:

Format I: Double Operand

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Double Operand Instructions

Format II: Single Operand

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Single Operand Instructions

Format III: Jump Instruction

• Jump instructions are used to direct program flow to another part of the program (by changing the PC).
• The condition on which a jump occurs depends on the Condition field consisting of 3 bits:
• JNZ/JNE 000: jump if not equal (Z = 0)
• JZ/JEQ 001: jump if equal (Z = 1)
• JNC/JLO 010: jump if no carry (C = 0)
• JC/JHS 011: jump if carry (C = 1)
• JN 100: jump if negative (N = 1)
• JGE 101: jump if greater than or equal (N = V)
• JL 110: jump if lower (N ≠ V)
• JMP 111: unconditional jump

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Jump Instructions

Quiz 3.2

1. How are the sixteen MSP430 registers the same?

​

• How do they differ?

​

• What does 8-bit addressibility mean?

​

• Why does the MSP430 have a 16-bit data bus?

​

• What does the “addc.w r11,r12” instruction do?

​

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MSP430 Addressing Modes

Addressing Modes

• MSP430 has 4 basic ways to get an operand.
• Address mode: Register + Mode

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Addressing Modes

Addressing Modes (C, C++)

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Source Addressing Modes (As)

• The MSP430 has four basic addressing modes for the source address (As):
• 00 = Rs - Register (+0 cycles)
• 01 = index(Rs) - Indexed Register (+2 cycles)
• 10 = @Rs - Register Indirect (+1 cycle)
• 11 = @Rs+ - Indirect Auto-increment (+1 cycle)
• When used in combination with registers R0-R3, three additional source addressing modes are available:
• label - PC Relative, index(PC) (+2 cycles)
• &label – Absolute, index(SR) (+2 cycles)
• #n – Immediate, @PC+ (+1 cycle)
• Constant generator with R2 and R3:
• #-1, 0, 1, 2, 4, 8 (+0 cycles)
• 30% code savings

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Addressing Modes

Destination Addressing Modes (Ad)

• There are only two basic addressing modes for the destination address (Ad):
• 0 = Rd - Register (+0 cycles)
• 1 = index(Rd) - Indexed Register (+2 cycles)
• When used in combination with registers R0/R2, two additional destination addressing modes are available:
• label - PC Relative, index(PC) (+2 cycles)
• &label – Absolute, index(SR) (+2 cycles)
• Storing result in memory adds an additional clock cycle.

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Addressing Modes

Instruction Length and Cycles

Instruction Length

• 1 word (2 bytes) for instruction:
• Format I:
• Format II:
• Format III:

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Instruction Length

Instruction Clock Cycles

• Generally, 1 cycle per memory access:
• 1 cycle to fetch instruction word
• +1 cycle if source is @Rn, @Rn+, or #Imm
• +2 cycles if source uses indexed mode
• 1^st to fetch base address
• 2^nd to fetch source
• Includes absolute and symbolic modes
• +2 cycles if destination uses indexed mode
• +1 cycle if writing destination back to memory
• Additionally
• +1 cycle if writing to PC (R0)
• Jump instructions are always 2 cycles

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MSP430 Clock Cycles

Quiz 3.3

• What is the length (in words) and cycles for each of the following instructions?

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1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

Instruction Operand Access

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1 ;****************************************************

2 .cdecls C,"msp430.h" ; MSP430

3 000 .text

4

5 8000 540A reset: add.w r4,r10 ; r10 = r4 + r10

6 8002 541A add.w 6(r4),r10 ; r10 = M(r4+6) + r10

8004 0006

7 8006 542A add.w @r4,r10 ; r10 = M(r4) + r10

8 8008 543A add.w @r4+,r10 ; r10 = M(r4++) + r10

9 800a 501A add.w cnt,r10 ; r10 = M(cnt) + r10

800c 0012

10 800e 521A add.w &cnt,r10 ; r10 = M(cnt) + r10

8010 801E

11 8012 503A add.w #100,r10 ; r10 = 100 + r10

8014 0064

12 8016 531A add.w #1,r10 ; r10 = 1 + r10

13 8018 5090 add.w cnt,var ; var = M(cnt) + M(var)

801a 0004

801c 0004

14

15 801e 0000 cnt: .word 0

16 8020 0000 var: .word 0

Addressing Modes

40

40

The Instruction Cycle

• INSTRUCTION FETCH
• Obtain the next instruction from memory
• DECODE
• Examine the instruction, and determine how to execute it
• SOURCE OPERAND FETCH
• Load source operand
• DESTINATION OPERAND FETCH
• Load destination operand
• EXECUTE
• Carry out the execution of the instruction
• STORE RESULT
• Store the result in the designated destination

Not all instructions require all six phases

Instruction Cycle

00 = Register Mode

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Addressing Modes

Registers

CPU

add.w r4,r10 ;r10 = r4 + r10

R10

R4

IR

0x540a

PC

ALU

1 Cycle Instruction

01 = Indexed Mode

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Addressing Modes

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

add.w 6(r4),r10 ;r10 = M(r4+6) + r10

0x0006

R10

R4

IR

0x541a

PC

ALU

3 Cycle Instruction

10 = Indirect Register Mode

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Addressing Modes

Registers

Address Bus

Data Bus (+1 cycle)

CPU

add.w @r4,r10 ;r10 = M(r4) + r10

R10

R4

IR

0x542a

PC

ALU

2 Cycle Instruction

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Addressing Modes

Registers

Data Bus (+1 cycle)

CPU

11 = Indirect Auto-increment Mode

add.w @r4+,r10 ;r10 = M(r4+) + r10

R10

R4

IR

PC

0x543a

ALU

2 Cycle Instruction

Addressing Mode Variations

• Indexed Register
• xxxx(PC) = Symbolic (PC Relative)
• xxxx(SR) = Absolute (SR = R2 = 0)
• Constants
• @SR = 4
• @SR+ = 8
• R3 = 0
• xxxx(R3 ) = 1
• @R3 = 2
• @R3+ = -1

​

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ISA

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Addressing Modes

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

01 w/R0 = Symbolic Mode (PC Relative)

cnt

add.w cnt,r10 ;r10 = M(cnt) + r10

0x000c

R10

IR

0x501a

PC

ALU

3 Cycle Instruction

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Addressing Modes

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

cnt

01 w/R2 = Absolute Mode

0000

add.w &cnt,r10 ;r10 = M(cnt) + r10

0xc018

R10

IR

0x521a

PC

ALU

3 Cycle Instruction

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Addressing Modes

Registers

CPU

11 w/R0 = Immediate Mode

add.w #100,r10 ;r10 = 100 + r10

R10

IR

PC

0x503a

0x0064

ALU

2 Cycle Instruction

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Addressing Modes

Registers

CPU

Constant Generator

add.w #1,r10 ;r10 = #1 + r10

R10

IR

PC

0x531a

ALU

1 Cycle Instruction

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Addressing Modes

Registers

Address Bus

Data Bus (+1 cycle)

Data Bus (+1 cycle)

CPU

Three Word Instruction

cnt

add.w cnt,var ;var = M(cnt) + M(var)

0x000c

var

0x0218

IR

0x5090

PC

ALU

6 Cycle Instruction

Processor Speed

• MCLK – Master Clock
• Most instruction phases require a clock cycle
• No clock, no instruction execution
• CPI – Cycles Per Instruction
• Average number of clock cycles per complete instruction.
• MIPS – Millions of Instructions per Second (MIPS)
• Characterizes a processor’s performance
• MIPS = MCLK / CPI.
• Faster Clock speed ≠ faster computer

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Instruction Clock Cycles

Quiz 3.4

• Given a 1.2 MHz processor, what value for DELAY would result in a ≈1/4 second delay?

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DELAY .equ

​

mov.w #DELAY,r12 ; 2 cycles

​

delay1: mov.w #1000,r15 ; 2 cycles

​

delay2: sub.w #1,r15 ; 1 cycle

jne delay2 ; 2 cycles

sub.w #1,r12 ; 1 cycle

jne delay1 ; 2 cycles

?

Disassembling Instructions

How to Disassemble MSP430 Code

1. Begin with a “PC” pointing to the first word in program memory.

2. Retrieve instruction word and increment PC by 2.

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Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

How to Disassemble MSP430 Code

3. List the instruction mnemonic using the opcode (bits 12-15).

4. Append “.b” or “.w” using the b/w bit when appropriate (0=w, 1=b).

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0100 0000 0011 0001

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

How to Disassemble MSP430 Code

5. If double operand instruction, decode and list source operand. (If

necessary, fetch operand from memory and increment PC by 2.)

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Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0 0 11 0001

.w

mov

How to Disassemble MSP430 Code

6. If single or double operand instruction, decode and list destination

operand.

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Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0 0 11 0001

.w

mov

0x0400

#

How to Disassemble MSP430 Code

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0100 0000 1011 0010

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

…Retrieve instruction word, increment PC by 2, list mnemonic, and operand size.

How to Disassemble MSP430 Code

ISA

59

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1 0 11 0010

…Retrieve immediate source operand and increment PC by 2.

mov

.w

How to Disassemble MSP430 Code

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Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1 0 11 0010

…Retrieve absolute destination operand and increment PC by 2.

mov

.w

0x5a80

#

How to Disassemble MSP430 Code

ISA

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0100 0010 0111 1111

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

…Retrieve instruction word, increment PC by 2, list mnemonic, and operand size.

How to Disassemble MSP430 Code

ISA

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0100 0010 0 1 11 1111

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

…Use constant generator R2 for source operand.

mov

.b

How to Disassemble MSP430 Code

ISA

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0100 0010 0 1 11 1111

mov

.b

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

…Use register mode for destination operand.

#8

How to Disassemble MSP430 Code

ISA

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0001 0010 1011 0000

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

0100 0010 0111 1111

…Retrieve instruction word, increment PC by 2, list mnemonic, (but no operand size is used.)

How to Disassemble MSP430 Code

ISA

65

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

0100 0010 0111 1111

000100101 0 11 0000

…Retrieve immediate destination operand from memory and increment PC by 2.

call

.w

How to Disassemble MSP430 Code

ISA

66

.w

0011 1111 1111 1100

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

0100 0010 0111 1111

…Retrieve instruction word, increment PC by 2, and list mnemonic.

0001 0010 1011 0000

How to Disassemble MSP430 Code

ISA

67

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

0100 0010 0111 1111

001111 1111111100

…Calculate destination address by sign extending the least significant 10 bits, multiplying by 2, and adding the current PC.

jmp

0001 0010 1011 0000

.w

How to Disassemble MSP430 Code

ISA

68

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

0100 0010 0111 1111

1000 0011 0001 1111

…Retrieve instruction word, increment PC by 2, list mnemonic, and operand size.

0011 1111 1111 1100

0001 0010 1011 0000

.w

How to Disassemble MSP430 Code

ISA

69

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

0100 0010 0111 1111

1000 0011 0001 1111

…Use constant generator R3 for immediate source operand.

0011 1111 1111 1100

0001 0010 1011 0000

sub

.w

.w

How to Disassemble MSP430 Code

ISA

70

Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

0100 0010 0111 1111

1000 0011 0001 1111

…Use register mode for destination operand.

0011 1111 1111 1100

0001 0010 1011 0000

sub

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#1

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How to Disassemble MSP430 Code

ISA

71

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Instruction Disassembly

0xc000: 4031

0xc002: 0400

0xc004: 40b2

0xc006: 5a80

0xc008: 0120

0xc00a: 427f

0xc00c: 12b0

0xc00e: c012

0xc010: 3ffc

0xc012: 831f

0xc014: 23fe

0xc016: 4130

0100 0000 0011 0001

0100 0000 1011 0010

0100 0010 0111 1111

1000 0011 0001 1111

0010 0011 1111 1110

…Retrieve instruction word, increment PC by 2, and list mnemonic.