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INTRODUCTION

RISC-V is the free and open Instruction Set Architecture

Started as a “3 month project” at UC Berkeley in 2010.

Principal designers : Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovic.

May 2014 : The base user spec released after many iterations.

ORIGIN OF RISC-V

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What is RISC-V?

A high-quality, license-free, royalty-free RISC ISA.
Standard maintained by the non-profit RISC V foundation.
RISC-V is not…

-- A Company

-- it’s a CPU implementation

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RISC-V Foundation

RISC-V Foundation is a non-profit organization formed in August 2015 to publicly govern the ISA
Foundation Functions

-- Directs future development of ISA

-- Compliance tests

-- Promotion of the ISA>230 members representing a wide range of markets.

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Why RISC-V ?

Simplicity

Business

Model

Open Source

On par with modern CPU (performance, code density, power)

Business barriers to entry in the microprocessor industry have been enormous – hundreds of millions of dollars and hundreds of people working for years.
For decades we’ve relied on the economics of reducing the cost per transistor and wafer density toward increasing volumes to recoup investment.
Given the cost of entry, our industry was limited to few companies that could afford to be in the game.
That didn’t leave us with much to pick from and once we did, switching costs were high and we were locked in.
RISC-V has disrupted the entire business and technical status quo
Unconstrained opportunity means open:

Collaboration partners

Suppliers

Adjacent markets

Geographies

Open Source and global standards have taken substantial risk, investment, time, and constraints out of custom processor design.
When multiple stakeholders are invested across numerous domains, geographies, and implementations, you reduce the uncertainty of strategically choosing to build on RISC-V.

You have an invested global community
No one entity, person, or geography owns the technology. We all do.

This creates a cycle of growth

The building blocks we all rely on are in the public domain.
Multiple stakeholders continue to invest in RISC-V and grow the ecosystem,
The collective effect is building confidence and strategic investment in RISC-V.

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RISC-V Pipelined stages

Instruction Fetch (IF)
Instruction Decode (ID)
Execute (EXE)
Memory Access (MEM)
Write Back (WB)

RISC_V Architecture

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Verification Platform

uvm_seq_item : Generates test stimulus
uvm_sequencer : executes uvm_Seq_item, arbitration process between them.
uvm_driver : converts uvm_seq_item to pin wiggle signals
uvm_monitor : Monitors pin level behaviour on the DUT.
uvm_agent : encapsulates above uvm_components
uvm_scoreboard : Determine whether DUT behave properly or not.
Functional coverage : Ensures that implementation confirms to the specification.
uvm_env : Encapsulates uvm_agent, scoreboard and functional coverage

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Result

IF_ID

EXE_MEM

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Result

MEM_WB

Write Back

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Schematics Result

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Simulation Result

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Implementation

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Coverage Result

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Conclusion

The RISC V gives and open resource environment to allow the designer to tweak at a greater extent.
Here, 32-bit pipelined RISC V ISA is designed with Verilog Hardware Description Language (HDL) and synthesized.
Harnessing the System Verilog with verification methodology UVM, the correctness of the design is verified and functional coverage is obtained.

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