Prepared by�Mr.S. Arun�AP/EEE
19EEPE609 - DIGITAL SIGNAL PROCESSING
UNIT –I�INTRODUCTION
Classification of systems: Continuous, discrete, linear, causal, stability, dynamic, recursive, time variance; classification of signals: continuous and discrete, energy and power; mathematical representation of signals; spectral density; sampling techniques, quantization, quantization error, Nyquist rate, aliasing effect.
UNIT -II�DISCRETE TIME SYSTEM ANALYSIS
Z-transform and its properties, inverse z-transforms; difference equation – Solution by z- transform, application to discrete systems - Stability analysis, frequency response – Convolution – Discrete Time Fourier transform , magnitude and phase representation.
UNIT- III�DISCRETE FOURIER TRANSFORM & COMPUTATION
Discrete Fourier Transform- properties, magnitude and phase representation - Computation of DFT using FFT algorithm – DIT &DIF using radix 2 FFT – Butterfly structure.
UNIT IV �DESIGN OF DIGITAL FILTERS
FIR & IIR filter realization – Parallel & cascade forms. FIR design: Windowing Techniques – Need and choice of windows – Linear phase characteristics. Analog filter design – Butterworth and Chebyshev approximations; IIR Filters, digital design using impulse invariant and bilinear transformation Warping, pre warping.
UNIT V�DIGITAL SIGNAL PROCESSORS
Introduction – Architecture – Features – Addressing Formats – Functional modes - Introduction to Commercial DS Processors.
What is a DSP?
A specialized microprocessor for real-time DSP applications
Digital filtering (FIR and IIR)
FFT
Convolution, Matrix Multiplication etc
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Hardware used in DSP
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| ASIC | FPGA | GPP | DSP |
Performance | Very High | High | Medium | Medium High |
Flexibility | Very low | High | High | High |
Power consumption | Very low | low | Medium | Low Medium |
Development Time | Long | Medium | Short | Short |
Common DSP features
Harvard architecture
Dedicated single-cycle Multiply-Accumulate (MAC) instruction (hardware MAC units)
Single-Instruction Multiple Data (SIMD) Very Large Instruction Word (VLIW) architecture
Pipelining
Saturation arithmetic
Zero overhead looping
Hardware circular addressing
Cache
DMA
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Harvard Architecture
Physically separate memories and paths for instruction and data
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Single-Cycle MAC unit
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Can compute a sum of n-products in n cycles
Single Instruction - Multiple Data (SIMD)
A technique for data-level parallelism by employing a number of processing elements working in parallel
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Very Long Instruction Word (VLIW)
A technique for instruction-level parallelism by executing instructions without dependencies (known at compile-time) in parallel
Example of a single VLIW instruction:
F=a+b; c=e/g; d=x&y; w=z*h;
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CISC vs. RISC vs. VLIW
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Pipelining
DSPs commonly feature deep pipelines
TMS320C6x processors have 3 pipeline stages with a number of phases (cycles):
Fetch
Program Address Generate (PG)
Program Address Send (PS)
Program ready wait (PW)
Program receive (PR)
Decode
Dispatch (DP)
Decode (DC)
Execute
6 to 10 phases
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Direct Memory Access (DMA)
The feature that allows peripherals to access main memory without the intervention of the CPU
Typically, the CPU initiates DMA transfer, does other operations while the transfer is in progress, and receives an interrupt from the DMA controller once the operation is complete.
Can create cache coherency problems (the data in the cache may be different from the data in the external memory after DMA)
Requires a DMA controller
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Cache memory
Separate instruction and data L1 caches (Harvard architecture)
Cache coherence protocols required, since most systems use DMA
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DSP vs. Microcontroller
DSP
Harvard Architecture
VLIW/SIMD (parallel execution units)
No bit level operations
Hardware MACs
DSP applications
Microcontroller
Mostly von Neumann Architecture
Single execution unit
Flexible bit-level operations
No hardware MACs
Control applications
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