Module 4

VLSI Design – 18EC72

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Sequential Circuit Design

((10.1 and 10.3.1 to 10.3.4 of TEXT2))

Outline

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• Introduction
• Circuit Design for latches and Flip-flops.

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Introduction

• What is sequential circuit ? Purpose of sequential circuit.
• Examples for sequential circuits.
• Static circuits refer to gates that have no clock input, such as complementary CMOS, pseudo-nMOS, or pass transistor logic.
• Dynamic circuits refer to gates that have a clock input, especially domino logic.
• A sequencing element with static storage employs some sort of feedback to retain its output value indefinitely. An element with dynamic storage generally maintains its value as charge on a capacitor that will leak away if not refreshed for a long period of time.

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Circuit Design of Latches and Flip-flops

• Conventional CMOS latches are built using pass transistors or tristate buffers to pass the data while the latch is transparent and feedback to hold the data while the latch is opaque.
• Many latches accept reset and/or enable inputs. It is also possible to build logic functions into the latches to reduce the sequencing overhead.
• The True Single Phase Clocking (TSPC) technique uses a single clock with no inversions to simplify clock distribution. The Klass Semidynamic Flip-Flop (SDFF) is a fast flip-flop using a domino-style input stage. Differential flip-flops are good for certain applications.

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��Conventional CMOS latches : Transparent latches�

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��Conventional CMOS latches : Transparent latches�

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Conventional CMOS Flip-Flops

• Dynamic inverting flip-flop built from a pair of back-to-back dynamic latches

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• Adds feedback and another inverter to produce a noninverting static flip-flop

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Transmission gate and NORA dynamic flip-flops

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Flip-flop with two-phase nonoverlapping clock

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Pulsed latches

• A pulsed latch can be built from a conventional CMOS transparent latch driven by a brief clock pulse.
• The pulsed latch is faster than a regular flip-flop because it involves a single latch rather than two and because it allows time borrowing.
• It can also consume less energy, although the pulse generator adds to the energy consumption
• Drawback : Increased hold time.

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Pulse generators

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Resettable Latches and Flip-flops

• Two types of reset: synchronous and asynchronous.
• Asynchronous reset forces Q low immediately, while synchronous reset waits for the clock.
• Synchronous reset signals must be stable for a setup and hold time around the clock edge while asynchronous reset is characterized by a propagation delay from reset to output.
• Synchronous reset simply requires ANDing the input D with reset. Asynchronous reset requires gating both the data and the feedback to force the reset independent of the clock.

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Symbol and Synchronous Reset

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Asynchronous Reset

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Flip-flop with asynchronous set and reset

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Dynamic Logic Circuits

(9.1, 9.2, 9.4 to 9.5 of TEXT1)

Outline

• Introduction
• Basic Principles of Pass Transistor Circuits.
• Synchronous Dynamic Circuit Techniques.
• Dynamic CMOS Circuit Techniques.

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Introduction

• What are the disadvantages of Static logic circuits?

Merits of dynamic logic Implementation :

• The capability of temporarily storing a state, i.e., a voltage level, at a capacitive node allows us to implement very simple sequential circuits with memory functions.
• Also, the use of common clock signals throughout the system enables us to synchronize the operations of various circuit blocks. As a result, dynamic circuit techniques lend themselves well to synchronous logic design.

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Continued:

• Dynamic logic implementation of complex functions generally requires a smaller silicon area than does the static logic implementation.
• The power consumption which increases with the parasitic capacitances, the dynamic circuit implementation in a smaller area will, in many cases, consume less power than the static counterpart, despite its use of clock signals.

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Dynamic D-latch

• When the clock is high (CK = 1), the pass transistor turns on. The capacitor C, is either charged up, or charged down through the pass transistor MP, depending on the input (D) voltage level. The output (Q) assumes the same logic level as the input.
• When the clock is low (CK = 0), the pass transistor MP turns off, and the capacitor C is isolated from the input D. Since there is no current path from the intermediate node X to either VDD or ground, the amount of charge stored in C. during the previous cycle determines the output voltage level Q.

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Basic principles of Pass Transistor Circuits

• Basic building block for nMOS dynamic logic, which consists of an nMOS pass transistor driving the gate of another nMOS transistor

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Basic principles of Pass Transistor Circuits

• Logic 1 transfer : Assume that the soft node voltage is equal to 0 initially, i.e., Vx(t = 0) = 0 V. A logic " 1" level is applied to the input terminal, which corresponds to i = VOH = VDD. Now, the clock signal at the gate of the pass transistor goes from 0 to VDD at t = 0. It can be seen that the pass transistor MP starts to conduct as soon as the clock signal becomes active and that MP will operate in saturation throughout this cycle since VDS = VGS. Consequently, VD > VGS – VT

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Equivalent circuit for the logic " 1 " transfer event

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Basic principles of Pass Transistor Circuits

Variation of V as a function of time during logic "I" transfer

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Node voltages in a pass-transistor chain during the logic " 1 " transfer

Basic principles of Pass Transistor Circuits

Node voltages during the logic " 1 " transfer, when each pass transistor is driving another pass transistor.

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Basic principles of Pass Transistor Circuits

Logic 0 transfer:

Assume that the soft-node voltage V is equal to a logic " 1 " level initially, i.e., V(t = 0) = Vm = (VDD- VTn). A logic "" level is applied to the input terminal, which corresponds to V.n = 0 V. Now, the clock signal at the gate of the pass transistor goes from 0 to VDD at t = 0. The pass transistor MP starts to conduct as soon as the clock signal becomes active, and the direction of drain current flow through MP will be opposite to that during the charge-up (logic " 1 " transfer) event. The intermediate node X will now correspond to the drain terminal of MP and that the input node will correspond to its source terminal. With VGS = VDD and VDS = Vmax, it can be seen that the pass transistor operates in the linear region throughout this cycle, since VDS < VGS - VTn.

Equivalent circuit for the logic "0" transfer event.

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Basic principles of Pass Transistor Circuits

Variation of V as a function of time during logic “0" transfer

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Charge leakage

• Dynamic Logic Circuits during the active clock phase and that now both the input voltage Vn and the clock are equal to 0 V. The charge stored in Cx will gradually leak away, primarily due to the leakage currents associated with the pass transistor.

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Equivalent circuit for analyzing charge leakage process

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Synchronous dynamic circuit techniques

• Multi-stage pass transistor logic driven by two nonoverlapping clocks

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Nonoverlapping clock signals used for two-phase synchronous operation.

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Three stages of a depletion-load nMOS dynamic shift register circuit driven with two-phase clocking.

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Operation of Shift register

• During the active phase of clock signal1 the input voltage level V is transferred into the input capacitance C.
• Thus, the valid output voltage level of the first stage is determined as the inverse of the current input during this cycle.
• When clocksignal2 becomes active during the next phase, the output voltage level of the first stage is transferred into the second stage input capacitance Cn 2, and the valid output voltage level of the second stage is determined.
• During the active clocksignal2 phase, the first-stage input capacitance continues to retain its previous level via charge storage.
• When clocksignal1 becomes active again, the original data bit written into the register during the previous cycle is transferred into the third stage, and the first stage can now accept the next data bit.

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Depletion-load nMOS implementation of synchronous complex logic.

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Enhancement-load dynamic shift register (ratioed logic).

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General circuit structure of ratioed synchronous dynamic logic

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Enhancement-load dynamic shift register (ratioless logic).

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General circuit structure of ratioless synchronous dynamic logic

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CMOS Transmission Gate Logic

• Basic two-phase synchronous logic circuit principle, in which individual logic blocks are cascaded via clock-controlled switches, can easily be adopted to CMOS structures.
• Static CMOS gates are used for implementing the logic blocks, and CMOS transmission gates are used for transferring the output levels of one stage to the inputs of the next stage.
• Each transmission gate is actually controlled by the clock signal and its complement. As a result, two-phase clocking in CMOS transmission gate logic requires a total of four clock signals are generated and routed throughout the circuit.

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CMOS Transmission Gate Logic�

• The operation of CMOS dynamic logic relies on charge storage in the parasitic input capacitances during the inactive clock cycles.
• To illustrate the basic operation principles, the fundamental building block of a dynamic CMOS transmission gate shift register is shown in figure.

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Single-phase CMOS shift register, which is built by cascading identical units

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Dynamic CMOS logic (Precharge-Evaluate Logic)

• Dynamic CMOS circuit technique which allows us to significantly reduce the number of transistors used to implement any logic function.
• The circuit operation is based on first precharging the output node capacitance and subsequently, evaluating the output level according to the applied inputs.
• Both of these operations are scheduled by a single clock signal, which drives one nMOS and one pMOS transistor in each dynamic stage.

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Dynamic CMOS logic (Precharge-Evaluate Logic)

• Dynamic CMOS logic gate implementing a complex

Boolean function.

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Illustration of the cascading problem in dynamic CMOS logic.

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High performance Dynamic CMOS circuits

• Generalized circuit diagram of a domino CMOS logic gate.

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Cascaded domino CMOS logic gates

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Cascaded domino CMOS logic gates

• The limitation is that the number of inverting static logic stages in cascade must be even, so that the inputs of the next domino CMOS stage experience only 0 to 1 transitions during the evaluation. Cascading domino CMOS logic gates with static CMOS logic gates.

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Charge sharing between the output capacitance C and an intermediate node capacitance C2

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NORA CMOS Logic (NP-Domino Logic)

• In domino CMOS logic gates, all logic operations are performed by the nMOS transistors acting as pull-down networks, while the role of pMOS transistors is limited to precharging the dynamic nodes. As an alternative and a complement to nMOS-based domino CMOS logic, we can construct dynamic logic stages using pMOS transistors as well.

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NORA CMOS logic

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Text Books

• 1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang & Yosuf Leblebici, Third Edition, Tata McGraw-Hill.
• 2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste, and David Money Harris4th Edition, Pearson Education.

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• Note : Images and figures have been taken from prescribed textbooks.

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Reference Books

• 1. Adel Sedra and K. C. Smith, “Microelectronics Circuits Theory and Applications”, 6th or 7th Edition, Oxford University Press, International Version, 2009.
• 2. Douglas A Pucknell & Kamran Eshragian, “Basic VLSI Design”, PHI 3rd Edition, (original Edition – 1994).
• 3. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, TMH, 2007.

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