�Machine Instructions
COMPUTER ORGANIZATION
Prepared by
Mr. SUTHAGAR S/ AP/ ECE
Prepared By : Mr. SUTHAGAR S / AP / ECE
Machine Instructions and Programs
Prepared By : Mr. SUTHAGAR S / AP / ECE
Objectives
Prepared By : Mr. SUTHAGAR S / AP / ECE
Number, Arithmetic Operations, and Characters
Prepared By : Mr. SUTHAGAR S / AP / ECE
Signed Integer
Sign and magnitude
One’s complement
Two’s complement
4-bit machine word
16 different values can be represented
Roughly half are positive, half are negative
Prepared By : Mr. SUTHAGAR S / AP / ECE
Sign and Magnitude Representation
High order bit is sign: 0 = positive (or zero), 1 = negative
Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/-2n-1 -1
Two representations for 0
Prepared By : Mr. SUTHAGAR S / AP / ECE
One’s Complement Representation
Prepared By : Mr. SUTHAGAR S / AP / ECE
Two’s Complement Representation
like 1's comp
except shifted
one position
clockwise
Prepared By : Mr. SUTHAGAR S / AP / ECE
Binary, Signed-Integer Representations
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
+
1
-
2
+
3
+
4
+
5
+
6
+
7
+
2
-
3
-
4
-
5
-
6
-
7
-
8
-
0
+
0
-
1
+
2
+
3
+
4
+
5
+
6
+
7
+
0
+
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
1
+
2
+
3
+
4
+
5
+
6
+
7
+
0
+
7
-
6
-
5
-
4
-
3
-
2
-
1
-
b
3
b
2
b
1
b
0
Sign and
magnitude
1'
s complement
2'
s complement
B
V
alues represented
Binary, signed-integer representations.
Prepared By : Mr. SUTHAGAR S / AP / ECE
Addition and Subtraction – 2’s Complement
4
+ 3
7
0100
0011
0111
-4
+ (-3)
-7
1100
1101
11001
4
- 3
1
0100
1101
10001
-4
+ 3
-1
1100
0011
1111
If carry-in to the high
order bit =
carry-out then ignore
carry
if carry-in differs from
carry-out then overflow
Simpler addition scheme makes twos complement the most common
choice for integer number systems within digital systems
Prepared By : Mr. SUTHAGAR S / AP / ECE
2’s-Complement Add and Subtract Operations
1 1 0 1
0 1 1 1
0 1 0 0
0 0 1 0
1 1 0 0
1 1 1 0
0 1 1 0
1 1 0 1
0 0 1 1
1 0 0 1
0 1 0 1
1 1 1 0
1 0 0 1
1 1 1 1
1 0 0 0
0 0 1 0
0 0 1 1
0 1 0 1
4
+
(
)
2
-
(
)
3
+
(
)
2
-
(
)
8
-
(
)
5
+
(
)
+
+
+
+
+
+
1 1 1 0
0 1 0 0
1 0 1 0
0 1 1 1
1 1 0 1
0 1 0 0
6
-
(
)
2
-
(
)
4
+
(
)
3
-
(
)
4
+
(
)
7
+
(
)
+
+
(b)
(d)
1 0 1 1
1 1 1 0
1 0 0 1
1 1 0 1
1 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
0 0 1 1
1 0 0 1
1 0 1 1
1 0 0 1
0 0 0 1
0 0 1 0
1 1 0 1
0 1 0 1
0 0 1 0
0 0 1 1
5
-
(
)
2
+
(
)
3
+
(
)
5
+
(
)
2
+
(
)
4
+
(
)
2
-
(
)
7
-
(
)
3
-
(
)
7
-
(
)
6
+
(
)
3
+
(
)
1
+
(
)
7
-
(
)
5
-
(
)
7
-
(
)
2
+
(
)
3
-
(
)
+
+
-
-
-
-
-
-
(a)
(c)
(e)
(f)
(g)
(h)
(i)
(j)
Figure 2.4. 2's-complement Add and Subtract operations.
Page 31
Prepared By : Mr. SUTHAGAR S / AP / ECE
Overflow - Add two positive numbers to get a negative number or two negative numbers to get a positive number
5 + 3 = -8
-7 - 2 = +7
0000
0001
0010
0011
1000
0101
0110
0100
1001
1010
1011
1100
1101
0111
1110
1111
+0
+1
+2
+3
+4
+5
+6
+7
-8
-7
-6
-5
-4
-3
-2
-1
0000
0001
0010
0011
1000
0101
0110
0100
1001
1010
1011
1100
1101
0111
1110
1111
+0
+1
+2
+3
+4
+5
+6
+7
-8
-7
-6
-5
-4
-3
-2
-1
Prepared By : Mr. SUTHAGAR S / AP / ECE
Overflow Conditions
5
3
-8
0 1 1 1
0 1 0 1
0 0 1 1
1 0 0 0
-7
-2
7
1 0 0 0
1 0 0 1
1 1 0 0
1 0 1 1 1
5
2
7
0 0 0 0
0 1 0 1
0 0 1 0
0 1 1 1
-3
-5
-8
1 1 1 1
1 1 0 1
1 0 1 1
1 1 0 0 0
Overflow
Overflow
No overflow
No overflow
Overflow when carry-in to the high-order bit does not equal carry out
Prepared By : Mr. SUTHAGAR S / AP / ECE
Sign Extension
k copies of MSB
• • •
X
X ′
• • •
• • •
• • •
w
w
k
Prepared By : Mr. SUTHAGAR S / AP / ECE