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ODSA

Chiplet Business Challenges - Summary Presentation

Marek Hempel, Analog Devices

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Business Challenges - Company Presentations

Company

Presenters

Date

Recording Link

Meeting Minutes

Ventana

Travis Lanier

02/03/2023

Achronix

Nick Ilyadis

02/03/2023

eTopus

Kash

02/10/2023

JCET

Michael Lui

02/10/2023

NXP

Trent Uehling

02/17/2023

ADI

Marek Hempel

02/17/2023

Microchip

Timothy Pezarro

03/03/2023

Marvell

Mark Kuemerle

03/10/2023

AMD

Hemanth Dhavaleswarapu

03/10/2023

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Chiplet Challenges Summary

Ventena

Achronix

eTopus

JCET

NXP

ADI

Microchip

Marvell

AMD

Choice of Interface

Standard Chiplets

IP needed in several nodes

Exclusive KGD source ,no wiggle room;

No chiplets available

Quantify business case, how low in ASP

Ignorance around benefits of chiplets

Confidential Disclosure

System Partitioning

Final Product Responsibility

Packaging, standard or advanced

Die to Die std, UCIe or BoW

Heavy front-loading,

Business case for self development

IP Availability,

Cost benefit vs monolithic

Upfront-Cost of development

Keeping chiplet cost overhead low

Cost Model, how far down?

D2D Standard

KGD - Redundancy?

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Poor visibility (T2M, demand funnel, cycles, etc.).

Higher cost overhead packaging

KGD for RF

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3rd party chiplet availability

Open market 🡪 confidant model

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Chiplet security with secure systems

Hard IP - choices on node and metal stack

Root of Trust security

very little risk mitigation

Memory latency with side-by-side

Standardization e.g. link layer, power, etc.

Project schedule uncertainty

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Compute chiplet standardization

Chiplet Aspect Ratio, where are interfaces

Validation platform

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ESD Protection

Margin Stacking, Branding Obscurity

Generational reuse

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NUMA memory problems

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Open Marketplace?

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Scalable solutions, less BW than UCIe

Design secrets

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Best package, substrate option

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no central info resource

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Final Product Reliability/ responsibility

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Packaging std or adv

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low bandwidth D2D interface

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Standardization on LL, power, clocking

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BoW or UCIe,

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ESD Protection

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Main Issues by Count

  • Business
    • 6x Cost benefit vs monolithic, cost overhead
    • 3x Product schedule uncertainty, risk
    • 2x Up-Front Cost, capability of self-development
    • 2x Final Product Responsibility
    • 2x Confidential Disclosure

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  • Market Place
    • 3x Third Party Chiplet Availability
    • 2x No open marketplace yet

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  • Technical
    • 4x D2D Interface Choice
    • 3x Best packaging option std., adv.
    • 3x Standardization (Link layer, power, aspect ratio, etc.)
    • 3x IP availability in several nodes (D2D, validation, etc.)
    • 2x Known good die solutions
    • 2x Chiplet Security/ Root of Trust
    • 2x ESD Protection
    • 2x Less bandwidth, scalable interface

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Back Up

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Summary Ventena

  • Choice of Interface
  • Final Product Responsibility
  • Cost Model, how far down?
  • Chiplet security with secure systems
  • Compute chiplet architecture standardization
  • NUMA memory problems
  • Best package, substrate option

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Summary eTopus

Barriers:

  • IP needed? 🡪 NO CENTRAL INFO RESOURCE
  • Die to Die standards – which one?
  • KGD - Redundancy?
  • KYC – know your chiplet 🡪 Root of Trust security
  • Validation platform 🡪 no easy validation system exists
  • Open Marketplace?

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Todays slides share considerations for chiplet developers

Chiplet Market is booming seems like a great idea to develop one and be early to market for open chiplets.

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Todays slides share considerations for chiplet developers

Chiplet Market is booming seems like a great idea to develop one and be early to market for open chiplets.

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Barriers:

  • IP needed?
  • Die to Die standards – which one?
  • KGD - Redundancy?
  • KYC – know your chiplet?
  • Validation platform?
  • Open Marketplace?

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  • IP Needed
  • First what process ?
  • Next Foundry target ?
  • Packaging – standard, advanced?
  • Die2Die PHY ? Bump Map? Bump pitch ?
  • Link Layer ?
  • Speed ?
  • Power ?
  • Clocking – PLL - 2Ghz?

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  • NO CENTRAL INFO RESOURCE

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  • Die2Die standards
  • BOW and UCIe
  • BOW is more bare metal – more flexible
  • Next Gen BOW 2.0 is around the corner
  • UCIe is more fixed and less flexible

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  • Consider supporting both – if you want to increase

TAM chiplet on open market

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  • KGD – known good die
  • Chiplets economics work great when all the chiplets work
  • As no rework - economics become a disaster if one fails
  • Little secret ESD is being dramatically reduced for D2D

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  • We are working with a partner to run system level test on complete chiplet via Die2Die interface. Make sure chiplet is working fully in package. Can run @ power up & self test.

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  • Build in Redundancy into chiplet design – failure is not an option. Small chiplets especially critical. Not just at die2die interface. Advanced packaging more difficult to test.

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  • KYC – know your chiplets
  • As chiplets will be stored in die form
  • Supply chain is important but not infallible
  • Root of Trust security will be important

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  • We are working with a partner to secure our chiplets with unique identifier - technology is already out there

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  • Do consider root of trust or it or could limit your market

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  • Validation of your chiplet?
  • Currently no easy validation system exists
  • We hope to have one by mid 2024
  • Third party chiplets, ASICs, I/O chiplets

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Substrate

FPGA

Chiplet

PCIe

chiplet

UCIe

Chiplet

Space

BOW

Chiplet

Space

Substrate

Analog

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Chiplet

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  • Choices

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Single FPGA

Chiplet

Smaller FPGA Chiplets

Redundant Architecture

Any 2 of 3 must work

Program can be loaded depending on failure

Failure not an option

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  • Open Marketplace?
  • Ooops there is no OPEN chiplet market yet

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  • Coming soon …. Hopefully

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Chiplet Business Challenges Summary: JCET Group Co., Ltd.

What is the product (Chiplet, IP, tools, SW)?

Advanced-Node (up to 4nm) Chiplets packaged with JCET’s XDFOI™ technology; in a 2.xD configuration. Note: The Chiplets were consigned by the customer.

Product Status

High or Low Volume Manufacturing (HVM or LVM)

Target Customers Types

Fabless or OEM companies focusing on either of:

High-Performance Computing, 5G Communications, Consumer/Wearable, Autonomous-Driving Vehicles

Business Problems/Challenges Summary

  • Exclusive KGD source and thus no wiggle room;
  • Heavy front-loading with very little risk mitigation;
  • Poor visibility (T2M, demand funnel, cycles, etc.).

Additional Comment (Corporate PR Article)

https://www.jcetglobal.com/en/site/detailscon/882

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ADI Summary

  • Quantify business case, how low in ASP does it make Sense
  • IP Availability, which interface BoW or UCIe, low bandwidth D2D interface
  • KGD for RF
  • Standardization beyond D2D, e.g. link layer, power domains, etc.
  • Margin Stacking
  • Branding Obscurity
  • Design know-how / secrets around packaging
  • Final Product Reliability

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Challenges – Internal Chiplet Use

  • Cost
    • Cost overhead of chiplets in older node and low ASP products
      • Packaging cost, test cost, silicon area overhead
    • Hard to measure benefit of “reuse” internally
      • No data from other semi-industry

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  • Design
    • Question about UCIe vs BoW
    • IP availability in older nodes (e.g. 16 nm, 28 nm, 40 nm), especially for analog
    • Handling real-time data and sync, e.g. data stream for MIMO array
    • Optimized chiplet interfaces for lower performance/bandwidth apps
      • SPI equivalent but D2D optimized in term of power

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  • Test
    • KGD for analog chips (> 8GHz RF) can be challenging

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13 July 2022

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Challenges – External Use

  • Compatibility
    • Difficult to preemptively develop chiplets for general market
      • What link layer, what config of AMBA
      • Would be nice to have recommended settings (by Performance, Power, other)

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  • Business Aspects
    • Margin stacking of chiplets
      • possible solution: 3rd party aggregator?
    • Branding of products, if in “somebody else’s package”
    • Frameworks how to deal with scrap cost since 100% KGD is challenging

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  • Packaging
    • Domain expertise in package design (don’t want to share secret sauce)
    • Final trim, calibration is challenging if sold as chiplet

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  • Reliability
    • Final responsibility to customer in case of problems, who pays?

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13 July 2022

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ADI Summary

  • Quantify business case, how low in ASP does it make Sense
  • IP Availability, which interface BoW or UCIe, low bandwidth D2D interface
  • KGD for RF
  • Standardization beyond D2D, e.g. link layer, power domains, etc.
  • Margin Stacking
  • Branding Obscurity
  • Design know-how / secrets around packaging
  • Final Product Reliability

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