Adapted from Dr. Bassam Kahhaleh’ Slides by Prof. Iyad Jafar

Digital Logic

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Chapter 7

Registers and Counters

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Outline

• Registers
• Shift Registers
• Ripple Counters
• Synchronous Counters

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Registers

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Registers

• A register is basically a group of binary storage elements
• In theory, a register is sequential logic circuit which can be defined by a state table
• More often, think of a register as storing a vector of binary values
• Frequently used to perform simple
• data storage
• data movement
• processing operations

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Registers

• 4-bit register using D-FF
• I₃, I₂, I₁ and I₀ are loaded into the register on every rising edge of the clock

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Registers

A₃

A₂

A₁

A₀

Note: New data has to go in with every clock

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Registers with Parallel Load

• Control Loading the Register with New Data
• Add the Load (LD) input to decide when the data is loaded
• How?

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Registers with Parallel Load

• The load can be used to block/disable the clock!
• Should we block the “Clock” to keep the “Data”?

Delays the Clock

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Registers with Parallel Load

• Alternatively, use the LD to decide what happens on the edge: hold the old data or load the new data

D

Q

CLK

I₀

A₀

D

Q

I₁

A₁

D

Q

I₂

A₂

D

Q

I₃

A₃

Load

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Shift Registers

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Remember! Shift Left Operation

1

0

1

0

1

0

1

0

1

1

0

0

0

0

x

x

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Remember! Logical Shift Right Operation

1

0

1

0

1

0

1

0

0

1

1

0

0

0

x

x

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Remember! Arithmetic Shift Right Operation

1

0

1

0

1

0

1

1

1

1

1

1

1

1

x

x

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Shift Registers

• Shift Registers move data laterally within the register toward its MSB or LSB position
• In the simplest case, the shift register is simply a set of �D flip-flops connected in a row like this (4-bit shift register)

Serial�Input

Serial�Output

A

B

C

D

Parallel Output

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Shift Registers

CLK

SI

SO

Q₃

Q₂

Q₁

Q₀

Q₃

Q₂

Q₁

Q₀

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Universal Shift Register

• Performs the following operations
• Parallel-in Parallel-out
• Serial-in Serial-out
• Serial-in Parallel-out
• Parallel-in Serial-out

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Universal Shift Register

D₁

S₁�S₀

D₀

D₂

D₃

SI for SR

SI for SL

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Universal Shift Register

Q₃

Q₂

Q₁

Q₀

D₃

D₂

D₁

D₀

S₁

S₀

USR

SR_in

SL_in

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Real Stuff

• 74LS194
• 4-Bit Bidirectional Universal Shift Register

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Counters

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Counters

• Counters are sequential circuits which "count" through a specific state sequence.

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• They can count up, count down, or count through other fixed sequences.

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• Two distinct types are in common usage:
• Ripple Counters
• Synchronous Counters

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Types of Counter

Synchronous

Ripple

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Example 1 – 4-bit Ripple Counter

• Design a 4-bit ripple counter using T flip-flops

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• We need to know how to connect the FF inputs (T and clock)
• Investigate the counting pattern!

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Example 1 - 4-bit Ripple Counter

• Q0: toggles on every count
• Connect its clock input to the clock
• T0 =1
• Q1: toggles when Q0 change from 1 to 0
• Connect its clock to Q0
• T1 = 1
• Q2: toggles when Q1 change from 1 to 0
• Connect its clock to Q1
• T2 = 1
• Q3: toggles when Q2 change from 1 to 0
• Connect its clock to Q2
• T3 = 1

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Example 1 - 4-bit Ripple Counter

Q₀

Q₁

Q₂

Q₃

Delay accumulates towards the MSB

0

1

2

3

4

5

6

7

8

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Example 1 - 4-bit Ripple Counter Using D FFs

Q₃

Q₂

Q₁

Q₀

CLK

0

1

2

3

4

5

6

7

8

9

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Real Stuff

• 74HC4024
• 7-stage binary ripple counter

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Example 2

• Design the following synchronous counter using D FFs

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• Six states only!
• Unused states?

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Example 2

• Design the following synchronous counter

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Example 3 - Synchronous 4-bit Binary Counter

Design a 4-bit synchronous binary counter using JK FFs. The counter has an enable input to pause/resume counting.

• All FFs are synched to the clock.
• The Qs toggle; however, this should happen if Enable is 1 when the edge arrives.
• Q0 toggles on every edge if Enable is 1
• Connect the J and K inputs to Enable
• Q1 toggles when Enable is 1 and Q0 is 1 when the edge arrives
• Connect J and K to the AND of Q0 and Enable
• Q2 toggles when Enable = Q0 = Q1 = 1 when the edge arrives
• Connect J and K to the AND of Q0, Q1 and Enable
• Q3 toggles when Enable = Q0 = Q1 = Q2 = 1 when the edge arrives
• Connect J and K to the AND of Q0, Q1, Q2 and Enable

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Example 3 - Synchronous 4-bit Binary Counter

CLK

Enable

Q₃

Q₂

Q₁

Q₀

To Next Stage

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Example 4 - Up-Down Binary Counter

Up

Q₃

Q₂

Q₁

Q₀

Down

CLK

Design a 4-bit synchronous binary counter using T FFs. The counter has two inputs; up and down, to control counting order.

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Binary Counter with Parallel Load

Q₃

Q₂

Q₁

Q₀

LD

I₃

I₂

I₁

I₀

Count

CLR

Usually Asynchronous Clear

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Example 5

Q₃

Q₂

Q₁

Q₀

LD

I₃

I₂

I₁

I₀

Count

CLR

0

0

0

0

A₃

A₂

A₁

A₀

1

CLK

Count

The following counter can count 0,1,2, … 15, 0, 1, … . Modify it to

count up to 10 only.

Can you think of a different approach? How about using the CLR input?

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Example 5

Q₃

Q₂

Q₁

Q₀

LD

I₃

I₂

I₁

I₀

Count

CLR

0

0

0

0

A₃

A₂

A₁

A₀

1

CLK

Count

The following counter can count 0,1,2, … 15, 0, 1, … . Modify it to

count up to 10 only.

Can you think of a different approach? How about using the CLR input?

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