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Tools for the Open Chiplet Economy:�� Standardized Metrics for Chiplet Interconnect (PHY) Comparison

Shahab Ardalan, VP of Eng, Enosemi

Letizia Giuliano, VP Of Product Marketing & Management, Alphawave Semi

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Frequent dialogue:

Frequent dialogue

�

How much is the shoreline density ?

1 Tbps/mm

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Frequent dialogue:

Frequent dialogue

�

1 Tbps/mm

TX only or TX+RX?

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Die to Die Interface

Interposer, Substrate

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Objective

Accurately identify a comprehensive list of relevant parameters associated with the performance and functionality of the interface IP.
To propose a standardized and widely accepted method of measurement tailored specifically to these identified parameters
To establish a unified framework that not only provides a nuanced understanding of the intricacies inherent in Electrical PHY IP but also advocates for a consistent language and methodology in the measurement and assessment of these critical parameters.
This concerted effort is motivated by the overarching goal of fostering greater coherence, comparability, and interoperability within the field, thereby contributing to the advancement and standardization of practices specific to Electrical PHY IP

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Why do we need it?

A common method of parameter measurement and performance reporting in electronics interface IP is essential for several reasons:

Interoperability

Ease of Integration

Comparability

Reduced

Development Time

Quality

Assurance

Industry

Collaboration

Regulatory

Compliance

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Tools for the Open Chiplet Economy

In the Open Chiplet Economy, essential tools include

Chiplet Interface Standards
Collaborative Design Platforms
Chiplet Verification Suites
Interoperability Test Kits

Metric	Units
D2D Spec/Version	(N/A)
Data lane speed	Gbps
PHY Bandwidth (Rx + Tx)	Gbps
PHY Bandwidth per shoreline	Tbps/mm
Reach	mm
Power efficiency	pJ/bit
Packaging type	Std Pkg or Adv Pkg
Min bump pitch	um
BER	Ex: 1E-15
Latency T1	ns

A short performance table:

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Background

The workgroup started to collect data starting 2017 to compare different interface PHYs
Different FoM adopted to compare available interfaces and a comprehensive list of Interface IP published back in 2021-2022.
Eventually, team decided to focus on identifying a common set of parameters rather than collecting data.

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Interface Qualitative Attributes

Type (Serial or Parallel)
Clocking/Date Rate: (SDR/DDR/QDR ..)
Signaling: Diffrential / Single-Ended
Logical Link ( Unidirectional Simplex / Bidirectional Simplex / Duplex)
Signaling type (NRZ, PAM4)
IO swing type (rail2rail, partial)
Clocking (forwarded/recovered)
Termination
Maturity (Many vendors > IP avail > spec avail > spec under dev)
Silicon Status (None, Test-Chip,Product Prototype, Product Sampling, High Volume Man.)
publicly announced customers / refrence users
Open / Proprietary
Specification Access (fee-free / fee)
Organization if open
Reference (to standard, must if open)
Compliance to other PHY
packaging technology (organic, bridge, interposer, fanout, 3D)

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Link Parameters

Number of data lanes
Number of data wires
Number of clock wires
Number of other wires (high-speed)
Mandatory Side Band (nunber of lanes, if there is not, put zero) (number of other wires (low Speed)
Targeted speed per data lane

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Unit Unidirectional simplex link

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Reporting ½ of Area

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Section 2a: Unit simplex link parameters

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# of data lanes

# of data wires ( 2X Data Lane if it is differential)

Unidirectional Link

Bidirectional Link

# of clock wires

# of other wires

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Latency & BER

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	Data Rate	Latency	BER
Ser to Des	1 GTps	T0-A	BL0-A
Ser to Des	Max Supported Rate (DR0)	T0-B	BL0-B
Packet to Packet	1 GTps	T1-A	BL1-A
Packet to Packet	Max Supported Rate (DR1)	T1-B	BL1-B
With Retry	Max Supported Rate (DR2)	N/A	BL3

Packets

FEC

CRC

SER

TX

RX

DES

Packets

FEC

CRC

T1 & BL1

T0 & BL0

1GTps
Max Supported Rate

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Die Parameters

Proces Technology
Number of power supplies and values
IO swing value Vpp, single-ended
Min Data Bump spacing-x
Min Data Bump spacing-y
Unit Beach front per die
Unit Depth per die
Total (Tx + Rx + clocking) [Amortized, single pair] physical area (x-dim)
Total (Tx + Rx + clocking) [Amortized, single pair] physical area (y-dim)
How many TX/RX macro can share one clocking block
Max Stacked units
Number of substrate layers for reported edge density
Latency & BER
Reach

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Package Technology Enablers

Advanced Package

uBump 25-55um pitch |

Moderate-Low Yield

$$$

Standard Package

C4 bump 100-130um pitch |

High Yield

$

C4

Advanced Package

C4 bump 100-130um pitch | uBump 25-55um pitch

High-Moderate Yield

$$

C4

uBump

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List of Participant

Ahmad Tavakoli (Yorchip)

Anu Ramamurthy (Microchip)

Armin Tajalli (Kandou)

Bapi Vinnakota (OCP)

Boon Chong Ang (Intel)

Cliff Grossner (OCP)

Elad Alon (Blue Cheetah Analog)

James Wong (Palo Alto electron)

Kevin Donnelly (Eliyan)

Kevin Yee (Samsung)

Madhumita Sanyal (Synopsys)

Majid Foodeei (Kandou)

Quinn Jacobson ( CMU)

Shahab Ardalan (Enosemi)

Trent Uehling (NXP)

A big thank you to all active participants for their enthusiastic contributions.

Your valuable insights and technical discussions have greatly aided in identifying needed parameters and preparing the whitepaper.

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Example BoW and UCIe

Metric	Units	BoW (Std PKG)	BoW (Adv PKG)	UCIe (Std PKG)	UCIe (Adv PKG)
D2D Spec/Version	(N/A)	2.0	2.0	1.1	1.1
Data lane speed	Gbps	32	32	32	32
PHY Bandwidth (Rx + Tx)	Gbps	1024 over16-bit	1024 over 16bit	1024 for 16bit 2048 for 32bit	2048 for 32bit 4096 for 64bit
PHY Bandwidth per shoreline	Tbps/mm	2.068	13.653	1.8	5.2
Reach	mm	25	PKG dependent ( <5)	25	2
Power efficiency	pJ/bit	0.3-0.5	0.2-0.35	0.4-0.7	0.4-0.7
Packaging type	Std Pkg or Adv Pkg	Std Pkg	Adv Pkg	Std Pkg	Adv Pkg
Min bump pitch	um	Not define Typical = 110um	Not defined Typical = 45um	100-130	25-55
BER	Ex: 1E-15	1E-15	1E-15	1E-15	1E-15
Latency T0	ns	2ns	2ns	Comparable	Comparable

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Call for participation

Tuesdays @ 9:00am
Link to the existing PDF (draft) : http://tinyurl.com/2024D2D
Open for 30 days for feedback and comment

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