1 of 19

2 of 19

SERVER

OCP NIC Community Update�August 2024

�����Sub-group Project wiki: https://www.opencompute.org/wiki/Server/NIC�

Mailing List: https://ocp-all.groups.io/g/OCP-NIC

NIC3.0

3 of 19

Agenda

  • OCP Global Summit
  • Draft 1.4.7 Changes
  • SI update
  • Mechanical Updates

4 of 19

OCP Global Summit

  • October 15-17, 2024 San Jose, CA
  • 3 abstracts selected merge into 2 presentations
  • OCP Innovation Village OCP NIC demo accepted
    • Broadcom, Dell, Intel, Meta, Spirent submitted request and being assigned to same demo booth
    • Open to more participating companies

​

5 of 19

Spec updates

  • Version 1.4.7 draft
    • Flex I/O (Timing Pin) definition completed.
    • 0xC2 OEM Record completed
    • Added section for DSFF current sharing
    • PCIe Gen 6 channel requirements ratified
      • Conformance insertion loss = -7.0 dB at 16 GHz, adds informative limits
  • Please help review

​

  • Draft posted on wiki page:

https://www.opencompute.org/w/index.php?title=Server/NIC#Working_Draft_Docs

6 of 19

Flex I/O Pin Mapping

  • Timing pin definition completed
    • Aligns pin direction from RBT
    • TS_GPO changed to RSVD/NC in spec;
      • Time sensitive notifications from Baseboard to NIC can be done via in-band methods.

​

  • Future workstream discussions on RBT pins in timing mode.
    • Originally included to prevent HW Arbitration ring issues w/SFF Timing NIC in RBT baseboard.
    • 50 MHz required in all non-RBT baseboards.
    • Niche case?

​

GPO is now N/C

7 of 19

0xC0 Base OEM Record change

  • Remove call out for USB CDC-EEM
    • Detection is done at protocol level
    • No need to declare in OEM Record

​

  • Windows 11 supports CDC-NCM
  • Linux supports CDC EEM, ECM, and NCM

8 of 19

DSFF Current Sharing

  • Added DSFF requirement to balance current from both connectors

​

  • NIC side
    • Ensure power not to exceed 80 W per connector
    • Primary and Secondary balanced within 6%
    • ~150 W usable power (like LFF)

​

  • Baseboard side:
    • Should - provide symmetric power slots
    • If asymmetric, max power for DSFF is:
      • 2*min(Slot 0, Slot 1)
    • Local BMC aware of slot power envelopes

9 of 19

Spec Update Timeline

DSFF electrical complete

Timing pin addition complete

PCIe Gen 5, Gen 6 limits complete

Shock and Vibe Fixture (drawings almost complete)

DSFF Thermal Test Fixture (~October/November ‘24, more info next month)

​

All draft mechanical drawings in spec by end of August.

1.5.0 release candidate first week of September

1.5.0 published mid-September.

​

10 of 19

SI Update

  • SI workstream meeting series sunsetted
  • PCIe Gen 6 channel parameters are included in the current draft specification

​

  • Dell contributing DSFF CBB SI fixture, Gen 6 by default
  • Dual SFFs, same MMPXs used with Gen 5 fixtures
  • Routing two board options: micro-strip and stripline
  • Incorporating feedback from Broadcom and Intel
    • Includes moving the MMPX connectors farther apart to reduce serpentining
    • This has an adverse impact of increasing the trace length, but we should have plenty of IL available
    • We will do one final review and send for fabrication
    • Timeline is TBD but still expect samples prior to OCP global summit
  • Adding SMAs for the USB differential pair

​

11 of 19

Mechanical Updates

  • DSFF & TDSFF final assembly drawing complete
  • DSFF + M-FLW in chassis CAD model complete
    • Being used to generate multiple drawing and images for spec illustration
  • Final shock and vibe fixture configuration pending consensus
    • Most likely will be 4 on existing plate with modification

12 of 19

Mechanical Updates

  • Thermal section is TBD
  • Some content will be left as TBD for 1.5.0 of spec
    • i.e.: ejector latch faceplate, BOM table updates, thermal details
  • Joe working this week to populate drawings and images into spec
  • Goal is to have most required drawing and images added to the spec by end of next week
    • Allows 2 weeks for other edits and last minute changes to drawing/images before release first week of September

13 of 19

Backup slides

14 of 19

Spec updates

  • Version 1.4.5 released
    • DSFF Mechanical outline locked
    • Electrical complete for DSFF
    • PCIe Channel budget aligned -7.0 dB at 16 GHz for Gen 5

​

Release:

https://www.opencompute.org/w/index.php?title=Server/NIC#Released_Specification_Docs

15 of 19

Spec - 1.4.6 WIP Items

​

  • SI working group - PCIe Gen 6 spec limits for SFF & DSFF
    • Released for public comment/review
    • Conformance insertion loss = -7.0 dB at 16 GHz, adds informative limits
  • DSFF Mechanical Drawings / views
    • No notches in faceplate for internal lock
  • DSFF Shock and Vibe Fixture (drawings)
    • Should be backwards compatible with existing plate
  • DSFF Thermal Test Fixture (Dell Contribution)
  • DSFF PCIe Gen6 CBB (Dell Contribution)
    • In ECAD layout

16 of 19

Spec - New for draft 1.4.6 (in progress)

  • Add option for Flex I/O timing pins along card edge
    • Dell contributed on June 10th
    • Hardware traceable clocking sources
    • Add Telco clock profile capability (e.g. G.8265.1, G.8275.1, and G.8275.2)

​

  • NIC - HPM interface
    • 10 MHz with ePPS (default)
    • 10 MHz with separate 1PPS (alternate option)

​

  • Over-subscribes existing RBT pins
    • Default: isolated
  • Adds 0xC2 OEM Record for timing

17 of 19

Flex I/O Pin Mapping (WIP)

18 of 19

Flex I/O Examples (WIP)

19 of 19

Flex I/O 0xC2 OEM Record