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A Deeper Look into�RowHammer’s Characteristics �in Real Modern DRAM Chips

agyaglikci.github.io

safari.ethz.ch

Abdullah Giray Yaglikci

Ph.D. Candidate

SAFARI Live Seminar

17 January 2024

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DRAM: Dynamic Random Access Memory

1

DRAM stores the data-in-use

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DRAM: Dynamic Random Access Memory

2

DRAM stores the data-in-use

DRAM should be trustable�for reliability, security, and safety

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DRAM Organization

3

DRAM Chip

Bank

Chip I/O

DRAM Bank

Subarray

. . .

DRAM Subarray

Row Buffer

Bitline

…

Wordline

…

DRAM Cell

DRAM Row

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DRAM Operation

4

DRAM Subarray

Bitline

…

Wordline

…

DRAM Cell

Row Buffer

Row Activation: Fetch the row’s content into the row buffer

Column Access: Read/Write a column in the row buffer

Precharge: Disconnect the row from the row buffer

Wordline

Capacitor

Access transistor

Bitline

charge

leakage

paths

Refresh: Restores the capacitor voltage�with a time period called refresh window

I/O Circuitry

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The RowHammer Vulnerability

5

Row 0

Row 1

Row 2

Row 3

Row 4

Repeatedly opening (activating) and closing (precharging)

a DRAM row causes RowHammer bit flips in nearby cells

Row 2

open

Row 1

Row 3

Row 2

closed

Row 2

open

Row 1

Row 3

Row 0

Row 4

Row 2

closed

Victim Row

Aggressor Row

Row 2

open

Row 2

closed

Aggressor Row

DRAM Subarray

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DRAM Read Disturbance – Swimming Pool Analogy

6

Swimming in a lane disturbs nearby lanes

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DRAM Read Disturbance: A Prime Example

7

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Implications of DRAM Read Disturbance

8

Leak Private Information

Take Over a Computer

Data Loss or Corruption

Compromise Application Correctness

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DRAM Read Disturbance Worsens

Mitigations are becoming prohibitively expensive
More effective and efficient solutions are needed

9

DRAM chips are increasingly more vulnerable �to read disturbance with technology scaling

Technology Scaling

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Read Disturbance in DRAM

10

Increasing focus on exploiting, understanding, �and solving DRAM read disturbance

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Thesis Statement

11

Building a detailed understanding of�DRAM read disturbance

and

leveraging insights into

modern DRAM chips and memory controllers

enable researchers and engineers

to mitigate DRAM read disturbance

efficiently and scalably

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My Dissertation Works

A deeper look into RowHammer’s characteristics

Solutions to DRAM read disturbance

12

Temperature

Memory access patterns

Victim cell’s�physical location

Voltage

Throttling Unsafe Accesses

Parallelizing Preventive Actions

Leveraging

Heterogeneity

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Solutions to DRAM Read Disturbance

13

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A Deeper Look into RowHammer’s Characteristics

14







Voltage

Victim cell’s

physical�location

Memory�access

patterns

Temperature

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DRAM Testing Infrastructure

15

SoftMC (DRAM Bender) on a Xilinx Virtex UltraScale+ XCU200

Fine-grained control over DRAM commands,

timing parameters (±1.5ns), temperature (±0.5°C ),

and wordline voltage (±1mV)

*Olgun et al., "DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips,” in TCAD, 2023. [GitHub: https://github.com/CMU-SAFARI/DRAM-Bender]

*

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DRAM Testing Methodology

To characterize our DRAM chips at worst-case conditions:

Prevent sources of interference during core test loop

No DRAM refresh: to avoid refreshing victim row
No DRAM calibration events: to minimize variation in test timing
No RowHammer mitigation mechanisms: to observe circuit-level effects
Test for less than a refresh window (32ms) to avoid retention failures
Repeat tests for ten times

Worst-case access sequence
We use worst-case access sequence based on prior works’ observations
For each row, repeatedly access the two physically-adjacent rows �as fast as possible

16

To characterize our DRAM chips at worst-case conditions we take two measures:

[CLICK] First, we prevent external sources of interference such that our tests can run consistently as desired and without interruptions. To achieve this we disable:

[CLICK] DRAM refresh to avoid refreshing victim rows during a test,

[CLICK] DRAM calibration events to minimize variation in test timings

[CLICK] and RowHammer mitigation mechanisms to ensure that we can directly observe circuit-level bit flips

[CLICK] we also ensure that our RowHammer tests complete in less than a refresh window to prevent retention failures from interfering with our results

[CLICK] and we repeat our tests ten times to filter out the noise in measurements

[CLICK] Second, we issue the worst-case access sequence for inducing RowHammer bit flips based on observations from prior work

[CLICK] which suggest to repeatedly activate the two physically-adjacent rows as fast as possible

=========

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A Deeper Look into RowHammer’s Characteristics

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





Voltage

Victim cell’s

physical�location

Memory�access

patterns

Temperature

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Key Takeaways from Temperature Analysis

18







To ensure that a DRAM cell is not vulnerable to RowHammer,

we must characterize the cell at all operating temperatures

Key Takeaway 1

RowHammer vulnerability tends to worsen �as DRAM temperature increases

However, individual DRAM rows can exhibit behavior �different from the dominant trend

Key Takeaway 2

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Key Findings: Temperature

19

Temperature

Vulnerability to�Read Disturbance

DRAM read disturbance is more effective �within a temperature range

Vulnerable temperature range �varies across memory regions

A DRAM cell should be tested �at each possible operating temperature

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Impact of Temperature on DRAM Cells

The fraction of vulnerable DRAM cells, experiencing bit flips at all temperature levels within their vulnerable temperature range

20

Temperature

bit flips

Vulnerable Temperature Range

no bit flips

Mfr. A	Mfr. B	Mfr. C	Mfr. D
99.1%	98.9%	98.0%	99.2%

OBSERVATION 1

Most DRAM cells are vulnerable to RowHammer �throughout a continuous temperature range

Lower

Bound

Upper

Bound

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Impact of Temperature on DRAM Cells

21

Lower Bound (°C)

Upper Bound (°C)

Fraction of Vulnerable DRAM Cells

Different DRAM cells are vulnerable to RowHammer �within specific temperature ranges

Vulnerable �from 70°C to 85 ° C

Vulnerable

from 55°C to 60°C

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Impact of Temperature on DRAM Cells

22

Lower Bound (°C)

Upper Bound (°C)

29.8% of the cells experience bit flips �at all tested temperatures

OBSERVATION 2

A significant fraction of vulnerable DRAM cells �exhibit bit flips at all tested temperatures

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Impact of Temperature on DRAM Cells

23

0.2% of the cells experience bit flips �only at 70°C

Lower Bound (°C)

Upper Bound (°C)

OBSERVATION 3

A small fraction of all vulnerable DRAM cells are vulnerable �to RowHammer only in a very narrow temperature range

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Impact of Temperature on DRAM Rows

24

Temperature (°C)

Variation in

Bit Flip Counts

per DRAM Row

More cells experience bit flips as temperature increases

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Impact of Temperature on DRAM Rows

25

Temperature (°C)

Variation in Bit Flip Counts per DRAM Row

OBSERVATION 4

A DRAM row’s bit error rate can either increase or decrease�with temperature depending on the DRAM manufacturer

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Also in the Paper

26

The minimum activation count at which a victim row experiences a bit flip (HC_first) when temperature changes:

OBSERVATION 5

DRAM rows can show either higher or lower HC_first

when temperature increases

OBSERVATION 6

HC_first tends to generally decrease

as temperature change (ΔT) increases

OBSERVATION 7

The HC_first change (ΔHC_first) tends to be larger

as temperature change (ΔT) increases

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Contributions to Understanding RowHammer

Lois Orosa*, Abdullah Giray Yağlıkçı*, Haocong Luo, Ataberk Olgun, Jisung Park, Hasan Hassan, Minesh Patel, Jeremie S. Kim, and Onur Mutlu,�"A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses"�Proceedings of the 54th International Symposium on Microarchitecture�(MICRO), Virtual, October 2021.�[Slides (pptx) (pdf)] [Talk Video (21 minutes)]�[Short Talk Slides (pptx) (pdf)]�[Lightning Talk Slides (pptx) (pdf)] [Lightning Talk Video (1.5 minutes)]�[arXiv version]

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A Deeper Look into RowHammer’s Characteristics

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





Voltage

Victim cell’s

physical�location

Memory�access

patterns

Temperature

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Review: The RowHammer Vulnerability [Kim+, ISCA14]

29

Row 0

Row 1

Row 2

Row 3

Row 4

Repeatedly opening (activating) and closing (precharging)

a DRAM row causes RowHammer bitflips in nearby cells

Row 2

open

Row 1

Row 3

Row 2

closed

Row 2

open

Row 2

closed

Victim Row

Aggressor Row

Row 2

open

Row 2

closed

Aggressor Row

DRAM Subarray

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Key Takeaways�from Aggressor Row Active Time Analysis

As an aggressor row stays active longer,

victim DRAM cells become more vulnerable to RowHammer

Key Takeaway 3

RowHammer vulnerability of victim cells decreases

when the bank is precharged for a longer time

Key Takeaway 4

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Key Takeaways�from Aggressor Row Active Time Analysis

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Memory Access Patterns

Read disturbance is more effective

if the read memory region

stays active longer

State-of-the-Art

Our Finding

Minimum Row Access Count to Induce the First Bitflip

36%

reduction

Fewer reads cause a more significant read disturbance

when the read memory region stays active longer

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Memory Access Patterns�in Aggressor Row Active Time Analysis

Baseline access pattern:

Increasing aggressor row active time:

Increasing bank precharged time:

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Time

Row A is active

Row B is active

Row A is active

Row B is active

Time

Row A is active

Time

Row A is active

Row B is active

Row A is active

Row B is active

Row A is active

Aggressor row active time

Bank�precharged time

Aggressor row active time

Aggressor row �active time

Bank�precharged time

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Increasing Aggressor Row Active Time

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Aggressor Row Active Time (ns)

Number of Bit Flips

per DRAM Row

As the aggressor row stays active longer, �more DRAM cells experience RowHammer bit flips

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Increasing Aggressor Row Active Time

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Aggressor Row Active Time (ns)

Number of Bit Flips

per DRAM Row

As the aggressor row stays active longer, �more DRAM cells experience RowHammer bit flips

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Increasing Aggressor Row Active Time

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Aggressor Row Active Time (ns)

Minimum Activation Count

to Observe a Bit Flip (HC_first)

Fewer activations are required to cause RowHammer bit flips when aggressor rows stay active for longer time

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Increasing Aggressor Row Active Time

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Aggressor Row Active Time (ns)

Minimum Activation Count

to Observe a Bit Flip (HC_first)

OBSERVATION 8

As the aggressor row stays active longer, �more DRAM cells experience RowHammer bit flips and they experience RowHammer bit flips at lower activation counts

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Also in the Paper

37

The variation in aggressor row active time’s effects across DRAM rows and the effect of increasing bank precharged time

OBSERVATION 9

As the aggressor row stays active longer, the RowHammer vulnerability consistently worsens across tested DRAM rows

OBSERVATION 10

As the bank stays precharged longer, fewer DRAM cells experience RowHammer bit flips and they experience RowHammer bit flips at higher activation counts

OBSERVATION 11

As the bank stays precharged longer, the RowHammer vulnerability consistently reduces across tested DRAM rows

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Contributions to Understanding RowHammer

Lois Orosa*, Abdullah Giray Yağlıkçı*, Haocong Luo, Ataberk Olgun, Jisung Park, Hasan Hassan, Minesh Patel, Jeremie S. Kim, and Onur Mutlu,�"A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses"�Proceedings of the 54th International Symposium on Microarchitecture�(MICRO), Virtual, October 2021.�[Slides (pptx) (pdf)] [Talk Video (21 minutes)]�[Short Talk Slides (pptx) (pdf)]�[Lightning Talk Slides (pptx) (pdf)] [Lightning Talk Video (1.5 minutes)]�[arXiv version]

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RowPress [ISCA 2023]

Haocong Luo, Ataberk Olgun, Giray Yaglikci, Yahya Can Tugrul, Steve Rhyner, M. Banu Cavlak, Joel Lindegger, Mohammad Sadrosadati, and Onur Mutlu,�"RowPress: Amplifying Read Disturbance in Modern DRAM Chips"�Proceedings of the 50th International Symposium on Computer Architecture (ISCA), Orlando, FL, USA, June 2023.�[Slides (pptx) (pdf)]�[Lightning Talk Slides (pptx) (pdf)]�[Lightning Talk Video (3 minutes)]�[RowPress Source Code and Datasets (Officially Artifact Evaluated with All Badges)]�Officially artifact evaluated as available, reusable and reproducible.�Best artifact award at ISCA 2023.

�

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RowPress A New DRAM Read Disturbance Phenomenon

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Row 0

Row 1

Row 2

Row 3

Row 4

Keeping a DRAM row open (activated)

causes RowPress bitflips in nearby cells

Row 2

open

Row 1

Row 3

Row 2

closed

Row 2

open

Row 1

Row 3

Row 2

closed

Victim Row

Aggressor Row

Row 2

open

Aggressor Row

DRAM Subarray

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RowPress vs. RowHammer

Instead of using a high activation count,�

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RowHammer

Aggressor Row

Open

Close

RowPress

Aggressor Row

Open

Close

We observe bitflips even with ONLY ONE activation �in extreme cases where the row stays open for 30ms

36ns, 47K activations to induce bitflips

7.8µs, only 5K activations to induce bitflips

�☞ increase the time that the aggressor row stays open

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RowPress [ISCA 2023]

Haocong Luo, Ataberk Olgun, Giray Yaglikci, Yahya Can Tugrul, Steve Rhyner, M. Banu Cavlak, Joel Lindegger, Mohammad Sadrosadati, and Onur Mutlu,�"RowPress: Amplifying Read Disturbance in Modern DRAM Chips"�Proceedings of the 50th International Symposium on Computer Architecture (ISCA), Orlando, FL, USA, June 2023.�[Slides (pptx) (pdf)]�[Lightning Talk Slides (pptx) (pdf)]�[Lightning Talk Video (3 minutes)]�[RowPress Source Code and Datasets (Officially Artifact Evaluated with All Badges)]�Officially artifact evaluated as available, reusable and reproducible.�Best artifact award at ISCA 2023.

�

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A Deeper Look into RowHammer’s Characteristics

43







Voltage

Victim cell’s

physical�location

Memory�access

patterns

Temperature

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Key Takeaways �from Spatial Variation Analysis

RowHammer vulnerability significantly varies

across DRAM rows and columns due to design-induced

and manufacturing-process-induced variation

Key Takeaway 5

The distribution of the minimum activation count to observe bit flips (HC_first) exhibits a diverse set of values in a subarray

but similar values across subarrays in the same DRAM module

Key Takeaway 6

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Spatial Variation in HC_first across Rows

DRAM Rows (sorted by reducing HC_first)

The minimum activation count to observe bit flips (HC_first) across DRAM rows:

Minimum Activation Count

to Observe a Bit Flip (HC_first)

The RowHammer vulnerability

significantly varies across DRAM rows

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Spatial Variation in HC_firstacross Rows

Min. Activation Count

to Observe a Bit Flip (HC_first)

DRAM Rows (sorted by reducing HC_first)

The RowHammer vulnerability

significantly varies across DRAM rows

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Spatial Variation in Hc_first across Rows

Minimum Activation Count

to Observe a Bit Flip (HC_first)

DRAM Rows (sorted by reducing HC_first)

OBSERVATION 12

A small fraction of DRAM rows are significantly more vulnerable to RowHammer than the vast majority of the rows

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Spatial Variation in BER across Columns

Column Index

Chip ID

Number of Bit Flips in a Column

OBSERVATION 13

Certain columns are significantly more vulnerable

to RowHammer than other columns

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Spatial Variation across Columns

Worse RowHammer Vulnerability

Larger Variation across DRAM Chips

16.7%

30.6%

High RowHammer vulnerability across all chips

High variation in vulnerability across chips

🡪 manufacturing-process-induced variation

🡪design-induced variation

0.0 0.2 0.4 0.6 0.8 1.0

1.0

0.5

0.0

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Spatial Variation in BER across Columns

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Spatial Variation across Columns

16.7%

50.8%

59.8%

30.6%

29.1%

OBSERVATION 14

Both manufacturing process and design

affect a DRAM column’s RowHammer vulnerability

Worse RowHammer Vulnerability

Larger Variation across DRAM Chips

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Spatial Variation in BER across Columns

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Also in the Paper

The minimum activation count at which a victim row experiences a bit flip (HC_first) across rows in a subarray and across subarrays in a DRAM module:

OBSERVATION 15

The most vulnerable DRAM row in a subarray

is significantly more vulnerable

than the other rows in the subarray

OBSERVATION 16

HC_first distributions of subarrays within a DRAM module

are significantly more similar to each other

than those of subarrays from different modules

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A Deeper Look into RowHammer’s Characteristics

52







Voltage

Victim cell’s

physical�location

Memory�access

patterns

Temperature

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DRAM Organization and Operation

53

DRAM Subarray

Bitline

…

Wordline

…

DRAM Cell

Row Buffer

DDR4 DRAM chips have two main voltage sources:

VDD (~1.2V) for DRAM array and I/O circuitry

VPP (~2.5V) for wordlines

VPP >> VDD so that access transistor conducts well

Wordline

Capacitor

Access transistor

Bitline

I/O Circuitry

VPP (~2.5V)

VDD

(~1.2V)

This is a simplified diagram of a DRAM cell, where the data is stored as capacitor voltage, and accessed through the access transistor [CLICK]

The cell charge is driven by using a nominal supply voltage of 1.2V denoted as VDD [CLICK]

A DRAM cell inherently exhibits several charge leakage paths [CLICK]

And requires to perform refresh operations to restore the capacitor voltage with a time period called refresh window.

[PAUSE]

To access a DRAM cell, [CLICK]

the memory controller must first open or activate the row to fetch the row’s data into the row buffer [CLICK]

A row is activated by asserting its wordline using a nominal wordline voltage of 2.5V, denoted as VPP [CLICK]

The READ and WRITE requests targeting the row are serviced from the row buffer [CLICK]

After all requests are serviced from the row, the memory controller must close or precharge the row in order to begin accessing data from another row. [CLICK]

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A Closer Look into RowHammer

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Low Voltage

Victim Row

Bitline

Low Voltage

Victim Row

Aggressor Row

Disturbance

High Voltage

Aggressor Row

Low Voltage

Victim Row

Low Voltage

time

Agressor Row

Wordline Voltage

Repeatedly toggling

wordline voltage

is the key to inducing RowHammer bit flips

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Our Hypothesis

55

Reducing wordline voltage

can reduce RowHammer vulnerability

without significantly affecting reliable DRAM operation

time

Wordline

Voltage

Reduction in Disturbance

Aggressor Row

Victim Row

Aggressor Row

Victim Row

Wordline

Bitline

Wordline

Bitline

Weaker Channel�in Access Transistor

Strong Channel

Weaker Channel

time

Wordline

Voltage

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Our Goal

56

Understand how the wordline voltage (VPP) affects

RowHammer vulnerability

and reliable DRAM operation on real DRAM chips

DRAM Subarray

Bitline

…

Wordline

…

DRAM Cell

Row Buffer

I/O Circuitry

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DRAM Chips Tested

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Mfr.	# DIMMs	# Chips	Density	Die	Org.	Date
A (Micron)	1 4 3 2	8 64 24 16	4Gb 8Gb 4Gb 4Gb	- B F -	x8 x4 x8 x8	48-16 11-19 07-21
B (Samsung)	2 1 3 1 1 2	16 8 24 8 8 16	8Gb 8Gb 8Gb 4Gb 4Gb 8Gb	B C D E F	x8 x8 x8 x8 x8 x8	52-20 19-19 10-21 08-17 02-21
C (SK Hynix)	2 3 2 3	16 24 16 24	16Gb 4Gb 4Gb 8Gb	A B C D	x8 x8 x8 x8	51-20 02-21 48-20

272 DDR4 DRAM Chips

3 Major Manufacturers

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More Details in the Paper

Mfr.	# DIMMs	# Chips	Density	Die	Org.	Date
A (Micron)	1 4 3 2	8 64 24 16	4Gb 8Gb 4Gb 4Gb	- B F -	x8 x4 x8 x8	48-16 11-19 07-21
B (Samsung)	2 1 3 1 1 2	16 8 24 8 8 16	8Gb 8Gb 8Gb 4Gb 4Gb 8Gb	B C D E F	x8 x8 x8 x8 x8 x8	52-20 19-19 10-21 08-17 02-21
C (SK Hynix)	2 3 2 3	16 24 16 24	16Gb 4Gb 4Gb 8Gb	A B C D	x8 x8 x8 x8	51-20 02-21 48-20

3 Major Manufacturers

Full paper on arXiv: https://arxiv.org/abs/2206.09999

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Key Takeaway from RowHammer Analysis

Reducing wordline voltage reduces RowHammer vulnerability

15.2% (66.9% max) fewer bit flips occur
Activation count at which the first bit flip occurs increases by 7.4% (85.8% max)

Takeaway 1

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Wordline Voltage’s Effect on RowHammer

Wordline Voltage: VPP (V)

1.2

1.0

0.8

0.6

0.4

0.2

1.5 1.7 1.9 2.1 2.3 2.5

OBSERVATION 1

Fewer DRAM cells experience RowHammer bit flips�under reduced wordline voltage

BER reduces �as VPP reduces

Bit Error Rate

(Normalized to VPP=2.5V)

Wordline Voltage: VPP (V)

1.2

1.0

0.8

0.6

0.4

0.2

1.5 1.7 1.9 2.1 2.3 2.5

Different DRAM modules

Lower is better

Variation across DRAM rows

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Wordline Voltage’s Effect on RowHammer

Wordline Voltage: VPP (V)

1.5 1.7 1.9 2.1 2.3 2.5

OBSERVATION 2

Reducing wordline voltage can cause more DRAM cells �to experience bit flips in a small fraction of rows (15.4%)

Bit error rate increases

Bit Error Rate

(Normalized to VPP=2.5V)

1.2

1.0

0.8

0.6

0.4

0.2

Lower is better

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Wordline Voltage’s Effect on RowHammer

Wordline Voltage: VPP (V)

1.5 1.7 1.9 2.1 2.3 2.5

1.3 1.6 1.9 2.2 2.5

1.5 1.7 1.9 2.1 2.3 2.5

1.2

1.0

0.8

0.6

0.4

0.2

OBSERVATION 1

Fewer DRAM cells experience RowHammer bit flips�under reduced wordline voltage

OBSERVATION 2

Reducing wordline voltage can cause more DRAM cells �to experience bit flips in a small fraction of rows (15.4%)

Bit Error Rate

(Normalized to VPP=2.5V)

Mfr. A

Mfr. B

Mfr. C

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Wordline Voltage’s Effect on RowHammer

Wordline Voltage: VPP (V)

Minimum Activation Count to Induce the First Bit Flip

(Normalized to VPP=2.5V)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

1.5 1.7 1.9 2.1 2.3 2.5

OBSERVATION 4

The first bit flip occurs at higher activation counts

as wordline voltage reduces

Min. activation count

to induce the first bit flip

increases as VPP reduces

Higher is better

Different DRAM modules

Variation across DRAM rows

Minimum Activation Count to Induce the First Bit Flip (Normalized to VPP=2.5V)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

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Wordline Voltage’s Effect on RowHammer

OBSERVATION 5

For a small fraction of rows (14.2%), the first bit flip occurs �at a smaller activation count as wordline voltage reduces

Min. activation count

to induce the first bit flip

reduces

Wordline Voltage: VPP (V)

1.5 1.7 1.9 2.1 2.3 2.5

Higher is better

Minimum Activation Count to Induce the First Bit Flip (Normalized to VPP=2.5V)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

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Wordline Voltage’s Effect on RowHammer

Wordline Voltage: VPP (V)

1.5 1.7 1.9 2.1 2.3 2.5

1.3 1.6 1.9 2.2 2.5

1.5 1.7 1.9 2.1 2.3 2.5

2.0

1.8

1.6

1.4

1.2

1.0

0.8

OBSERVATION 4

The first bit flip occurs at higher activation counts

as wordline voltage reduces

Minimum Activation Count �to Induce the First Bit Flip

(Normalized to VPP=2.5V)

OBSERVATION 5

For a small fraction of rows (14.2%), the first bit flip occurs �at a smaller activation count as wordline voltage reduces

Mfr. A

Mfr. B

Mfr. C

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Also in the Paper

Wordline voltage’s effect on RowHammer vulnerability

varies across different DRAM rows and manufacturers

OBSERVATION 3

Change in bit error rate �varies across different DRAM rows and manufacturers

OBSERVATION 6

Change in the activation count at which the first bit flip occurs varies across different DRAM rows and manufacturers

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Also in the Paper

OBSERVATION 6

HC_first increase with reduced wordline voltage varies �across different DRAM rows and manufacturers

OBSERVATION 3

BER reduction with reduced wordline voltage varies �across different DRAM rows and manufacturers

Wordline voltage’s effect on RowHammer vulnerability varies �across different DRAM rows and manufacturers

Full paper on arXiv: https://arxiv.org/abs/2206.09999

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Key Takeaway from RowHammer Analysis

Reducing wordline voltage reduces RowHammer vulnerability

15.2% (66.9% max) fewer bit flips occur
Activation count at which the first bit flip occurs increases by 7.4% (85.8% max)

Takeaway 1

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Our Hypothesis

Reducing wordline voltage

can reduce RowHammer vulnerability

without significantly affecting reliable DRAM operation

time

Wordline

Voltage

Reduction in Disturbance

Aggressor Row

Victim Row

Aggressor Row

Victim Row

Wordline

Bitline

Wordline

Bitline

Weaker Channel�in Access Transistor

Strong Channel

Weaker Channel

time

Wordline

Voltage

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Key Takeaways from DRAM Operation Analysis

208/272 tested DRAM chips reliably operate using nominal timing parameters �due to the built-in safety margins (guardbands)

64/272 tested DRAM chips can reliably operate �with longer row activation latency (24ns/15ns for 48/16 chips)

Takeaway 2

216/272 tested DRAM chips reliably operate using nominal refresh rate�due to the built-in safety margins (guardbands)

56/272 tested DRAM chips can reliably operate �using single-error-correction ECC or 2x the refresh rate for only 16.4% of rows

Takeaway 3

216/272 tested DRAM chips reliably operate using nominal refresh rate�due to the built-in safety margins (guardbands)

56/272 tested DRAM chips can reliably operate �using single-error-correction ECC or 2x the refresh rate for only 16.4% of rows

Takeaway 3

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Wordline Voltage’s Effect on Row Activation Latency

Wordline Voltage: VPP (V)

Row Activation

Latency (t_RCD)

25

20

15

10

5

1.5 1.7 1.9 2.1 2.3 2.5

OBSERVATION 7

Row activation latency increases with reduced wordline voltage

208 out of 272 DRAM chips complete row activation�before the nominal activation latency

Row activation latency�increases as V_PP reduces

Nominal activation latency�has a significant guardband

Different DRAM modules

Variation across DRAM rows

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Wordline Voltage’s Effect on Row Activation Latency

Wordline Voltage: VPP (V)

25

20

15

10

5

OBSERVATION 7

Row activation latency increases with reduced wordline voltage

208 out of 272 DRAM chips complete row activation�before the nominal activation latency

1.5 1.7 1.9 2.1 2.3 2.5

1.3 1.6 1.9 2.2 2.5

1.5 1.7 1.9 2.1 2.3 2.5

Row Activation

Latency (t_RCD)

Nom. t_RCD

Mfr. A

Mfr. B

Mfr. C

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Wordline Voltage’s Effect on Row Activation Latency

Wordline Voltage: VPP (V)

25

20

15

10

5

48 DRAM chips from Mfr A. reliably work with a row activation latency of 24 ns

16 DRAM chips from Mfr. B reliably work with a row activation latency of 15 ns

All DRAM chips from Mfr. C reliably work using the nominal latency of 13.5ns

1.5 1.7 1.9 2.1 2.3 2.5

1.3 1.6 1.9 2.2 2.5

1.5 1.7 1.9 2.1 2.3 2.5

Row Activation

Latency (t_RCD)

Nom. t_RCD

Mfr. A

Mfr. B

Mfr. C

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SPICE Simulation Methodology

Insights into wordline voltage’s affect on DRAM operation
22 nm transistor model
Monte-Carlo analysis with 5% variation and 10K iterations

Chang et al., "Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms," SIGMETRICS, 2018. [SPICE Model on GitHub]

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A Closer Look into Row Activation Latency

Row activation completes when the bitline voltage reaches a threshold (V_TH)
Reduced wordline voltage leads to a weaker channel in the access transistor

Bitline voltage takes longer to reach V_TH

Capacitor

Bitline

Wordline

Access transistor

Weaker

channel

OBSERVATION 8

Row activation latency increases

with reduced wordline voltage

Reducing

Wordline

Voltage

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Variation in Row Activation Latency

When wordline voltage is reduced from 2.5V to 1.9V:

The worst-case row activation latency is still lower than nominal value
The guardband reduces from 4.4% to 1.5% �as the worst-case latency increases from 12.9ns to 13.3ns

The SPICE simulation results are not identical with real chip observations

because the SPICE model cannot simulate a real DRAM chip’s exact behavior �without proprietary design and manufacturing information

Worst case t_RCD_min when VPP = 2.5V

Nominal row activation latency

Worst case t_RCD_min when VPP = 1.9V

OBSERVATION 9

SPICE simulation results agree with our observations�based on experiments on real chips

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Also in the Paper

Wordline voltage’s effect on DRAM charge restoration process

OBSERVATION 10

A DRAM cell’s capacitor voltage can saturate �at a lower voltage level when wordline voltage is reduced

OBSERVATION 11

A DRAM cell’s charge restoration latency (t_RAS_min) �can increase with reduced wordline voltage

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Also in the Paper

Wordline voltage’s effect on DRAM charge restoration process

OBSERVATION 10

A DRAM cell’s capacitor voltage can saturate �at a lower voltage level when wordline voltage is reduced

OBSERVATION 11

A DRAM cell’s charge restoration latency (t_RAS_min) �can increase with reduced wordline voltage

Full paper on arXiv: https://arxiv.org/abs/2206.09999

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Key Takeaways from DRAM Operation Analysis

208/272 tested DRAM chips reliably operate using nominal timing parameters �due to the built-in safety margins (guardbands)

64/272 tested DRAM chips can reliably operate �with longer row activation latency (24ns/15ns for 48/16 chips)

Takeaway 2

216/272 tested DRAM chips reliably operate using nominal refresh rate�due to the built-in safety margins (guardbands)

56/272 tested DRAM chips can reliably operate �using single-error-correction ECC or 2x the refresh rate for only 16.4% of rows

Takeaway 3

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Wordline Voltage’s Effect on DRAM Refresh

Refresh Window (ms)

Data Retention

Bit Error Rate

0.05

0.04

0.03

0.02

0.01

0

OBSERVATION 12

More DRAM cells tend to experience data retention bit flips

when wordline voltage is reduced

Data retention BER increases

as wordline voltage reduces

OBSERVATION 13

216 out of 272 DRAM chips reliably operate using nominal refresh rate�due to the built-in safety margins (guardbands)

64 256 1K 4K 16K

Different colors represent different wordline voltage levels

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Wordline Voltage’s Effect on DRAM Refresh

OBSERVATION 12

More DRAM cells tend to experience data retention bit flips

when wordline voltage is reduced

OBSERVATION 13

216 out of 272 DRAM chips reliably operate using nominal refresh rate�due to the built-in safety margins (guardbands)

Wordline Voltage’s Effect on DRAM Refresh

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Spatial Distribution of Data Retention Bitflips

There are no 64-bit words with more than one bit flip

A small fraction of DRAM rows contain erroneous words

OBSERVATION 14

Data retention errors can be avoided using single error correcting codes at the smallest refresh window that yields non-zero bit error rate

Fraction of DRAM Rows

Number of 64-bit data words with one bit flip

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Spatial Distribution of Data Retention Bitflips

There are no 64-bit words with more than one bit flip

A small fraction of DRAM rows contain erroneous words

OBSERVATION 15

Only a small fraction (16.4%/5.0%) of DRAM rows have erroneous words at the smallest refresh rate (64ms/128ms) that yields non-zero bit error rate

OBSERVATION 14

Data retention errors can be avoided using single error correcting codes at the smallest refresh window that yields non-zero bit error rate

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Key Takeaways from DRAM Operation Analysis

208/272 tested DRAM chips reliably operate using nominal timing parameters �due to the built-in safety margins (guardbands)

64/272 tested DRAM chips can reliably operate �with longer row activation latency (24ns/15ns for 48/16 chips)

Takeaway 2

216/272 tested DRAM chips reliably operate using nominal refresh rate�due to the built-in safety margins (guardbands)

56/272 tested DRAM chips can reliably operate �using single-error-correction ECC or 2x the refresh rate for only 16.4% of rows

Takeaway 3

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Takeaways from Voltage Study

Reduces RowHammer vulnerability

Bit error rate caused by a RowHammer attack reduces by 15.2% (66.9% max)
A row needs to be activated 7.4% more times (85.8% max) to induce the first bit flip

Increases row activation latency

More than 76% of the tested DRAM chips reliably operate using nominal timing parameters
Remaining 24% reliably operate with increased (up to 24ns) row activation latency

Reduces data retention time

80% of the tested DRAM chips reliably operate using nominal refresh rate
Remaining 20% reliably operate by

Using single error correcting codes
Doubling the refresh rate for a small fraction (16.4%) of DRAM rows

Reducing wordline voltage can reduce RowHammer vulnerability �without significantly affecting reliable DRAM operation

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We provide the first RowHammer characterization using real DRAM chips under reduced wordline voltage [CLICK]

Our experimental results using 272 real DRAM chips show that with reduced wordline voltage, [CLICK]

RowHammer vulnerability reduces such that Bit flips occur at larger activation counts and fewer DRAM cells experience RowHammer bit flip [CLICK]

Reducing wordline voltage can increase row activation latency

However, more than 75% of the tested DRAM chips reliably operate using nominal timing parameters

And remaining 25% still reliably operate with increased row activation latency [CLICK]

Reducing wordline voltage can worsen data retention time

However, 80% of the tested DRAM chips reliably operate using nominal refresh rate

And remaining 20% experience bit flips that

can be corrected using single error correcting codes

or can be avoided by doubling the refresh rate for a small fraction (16.4%) of DRAM rows [CLICK]

Therefore we concluded that reducing wordline voltage can reduce RowHammer vulnerability without significantly affecting reliable DRAM operation [CLICK]

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Contributions to Understanding RowHammer

Abdullah Giray Yağlıkçı, Haocong Luo, Geraldo F. de Oliviera, Ataberk Olgun, Minesh Patel, Jisung Park, Hasan Hassan, Jeremie S. Kim, Lois Orosa, and Onur Mutlu,�"Understanding RowHammer Under Reduced Wordline Voltage: �An Experimental Study Using Real DRAM Devices"�Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Baltimore, MD, USA, June 2022.�[Slides (pptx) (pdf)]�[Lightning Talk Slides (pptx) (pdf)]�[arXiv version]�[Talk Video (34 minutes, including Q&A)]�[Lightning Talk Video (2 minutes)]

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A Deeper Look into RowHammer’s Characteristics

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





Voltage

Victim cell’s

physical�location

Memory�access

patterns

Temperature

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Implications on Attacks and Defenses

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Our observations can be leveraged to craft

more effective RowHammer attacks

Our observations can be leveraged to design �more effective and efficient RowHammer defenses

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Attack Improvement 1: �Temperature-Dependent Trigger

Identify abnormal increase �in temperature to attack a data center during its peak hours

Precisely measure the temperature �to trigger an attack exactly at the desired temperature

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Temperature

70 °C

76.6%

of the cells^*

*Example fraction values from Mfr. C

0.4%

of the cells^*

Temperature

70 °C

Temperature

70 °C

0.4%

of the cells^*

1.

2.

In the second attack example, the attacker uses RowHammer to understand the DRAM chip’s current temperature [CLICK]

As an example, more than 76% of the vulnerable cells experience bit flips above 70 degrees Celsius for Mfr C. Focusing on these cells, an attacker can identify abnormal operating conditions that might occur in a data center during its peak hours. This information can be used to trigger an attack when the data center is under pressure[CLICK]

If it is important to measure temperature precisely, the attacker can focus on a smaller set of vulnerable cells that experience bit flips only in a narrow temperature range. For example, 0.4% of vulnerable cells experience bit flips only at 70 degrees Celsius in Mfr C. Using these cells, the attacker can precisely detect the temperature and trigger an attack accordingly [CLICK]

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Attack Improvement 1: �Temperature-Dependent Trigger

Identify abnormal increase �in temperature to attack a data center during its peak hours

Precisely measure the temperature �to trigger an attack exactly at the desired temperature

90

Temperature

70 °C

76.6%

of the cells^*

*Example fraction values from Mfr. C

0.4%

of the cells^*

Temperature

70 °C

Temperature

70 °C

0.4%

of the cells^*

1.

2.

Full paper on arXiv: https://arxiv.org/pdf/2210.04084.pdf

In the second attack example, the attacker uses RowHammer to understand the DRAM chip’s current temperature [CLICK]

As an example, more than 76% of the vulnerable cells experience bit flips above 70 degrees Celsius for Mfr C. Focusing on these cells, an attacker can identify abnormal operating conditions that might occur in a data center during its peak hours. This information can be used to trigger an attack when the data center is under pressure[CLICK]

If it is important to measure temperature precisely, the attacker can focus on a smaller set of vulnerable cells that experience bit flips only in a narrow temperature range. For example, 0.4% of vulnerable cells experience bit flips only at 70 degrees Celsius in Mfr C. Using these cells, the attacker can precisely detect the temperature and trigger an attack accordingly [CLICK]

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Attack Improvement 2: �Bypassing Defenses with Aggressor Row Active Time

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Reduces the minimum activation count to induce a bit flip by 36%

Bypasses defenses that do not account for this reduction

Time

Row A is active

Row B is active

Row A is active

Activating aggressor rows as frequently as possible:

Time

Row A is active

Row B is active

Keeping the aggressor rows active for a longer time:

36% reduction �in HC_first

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Defense Improvement 1:�Spatial Variation–Aware Read Disturbance Solutions

Significant variation in read disturbance vulnerability�across DRAM rows
Key Idea: To dynamically adapt the aggressiveness of existing solutions to the victim row’s read disturbance vulnerability
Key Results:

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Minimum Hammer Count to Induce the First Bitflip

Weighted Speedup

(Norm. to No Mitigation Baseline)

I will also explain two improvements for defense mechanisms in this slide, but you can find more in the paper [CLICK]

The first improvement leverages the variation across rows [CLICK]

We observe that 90% of the rows do not experience bit flips until the activation count reaches the double Hcfirst of the 10% of the rows.[CLICK]

Therefore, we can reduce the aggressiveness of defense mechanisms for 90% of the rows, which can reduce the area overheads of state-of-the-art defense mechanisms: [CLICK] BlockHammer and [CLICK] Graphene, by 33 and 80%, respectively [CLICK]

The second example leverages the variation in RowHammer vulnerability with temperature [CLICK]

We show that DRAM cells experience bit flips in bounded temperature ranges [CLICK]

To avoid bit flips, A DRAM row can be disabled when its cells are vulnerable to RowHammer at the current operating temperature [CLICK]

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Defense Improvement 1:�Spatial Variation–Aware Read Disturbance Solutions

Significant variation in read disturbance vulnerability�across DRAM rows
Key Idea: To dynamically adapt the aggressiveness of existing solutions to the victim row’s read disturbance vulnerability
Key Results:

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Minimum Hammer Count to Induce the First Bitflip

Weighted Speedup

(Norm. to No Mitigation Baseline)

Abdullah Giray Yağlıkçı, Yahya Can Tuğrul, Geraldo F. Oliveira, Ismail Emir Yuksel, Ataberk Olgun, Haocong Luo, and Onur Mutlu, "Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions,” to appear in HPCA, 2024.

I will also explain two improvements for defense mechanisms in this slide, but you can find more in the paper [CLICK]

The first improvement leverages the variation across rows [CLICK]

We observe that 90% of the rows do not experience bit flips until the activation count reaches the double Hcfirst of the 10% of the rows.[CLICK]

Therefore, we can reduce the aggressiveness of defense mechanisms for 90% of the rows, which can reduce the area overheads of state-of-the-art defense mechanisms: [CLICK] BlockHammer and [CLICK] Graphene, by 33 and 80%, respectively [CLICK]

The second example leverages the variation in RowHammer vulnerability with temperature [CLICK]

We show that DRAM cells experience bit flips in bounded temperature ranges [CLICK]

To avoid bit flips, A DRAM row can be disabled when its cells are vulnerable to RowHammer at the current operating temperature [CLICK]

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More Defense Implications in the Paper

Leveraging the similarity across subarrays in a DRAM module �can reduce the module’s profiling time for RowHammer errors

Monitoring and limiting the aggressor row active time from the memory controller can reduce the RowHammer vulnerability and make defenses more efficient

ECC schemes can target the non-uniform bit error distribution caused by design-induced variation across DRAM columns

Cooling DRAM chips can reduce overall bit error rate

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More Defense Implications in the Paper

Leveraging the similarity across subarrays in a DRAM module �to speed up profiling the module for RowHammer errors

Monitoring and limiting the aggressor row active time from the memory controller can reduce the RowHammer vulnerability and the defense cost

An ECC scheme can target the non-uniform bit error distribution caused by design-induced variation across DRAM columns

Cooling DRAM chips can reduce overall bit error rate

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Conclusion

Experimental study: 272 DRAM chips from four major manufacturers

Key Results: We provide takeaways based on novel observations

A RowHammer bit flip is more likely to occur

in a bounded range of temperature
if the aggressor row is active for longer time
in certain physical regions of the DRAM module under attack
when the aggressor row is activated using a higher voltage

Conclusion: Our novel observations can inspire and aid future work

Craft more effective attacks
Design more effective and efficient defenses

Denser DRAM chips are more vulnerable to RowHammer [CLICK]

And Understanding RowHammer is critical to find effective and efficient solutions. However, no rigorous study demonstrates how this vulnerability varies under different conditions [CLICK]

In this work, our goal is to provide insights into three fundamental properties of RowHammer that can be leveraged to design more effective and efficient attacks and defenses These three properties are [CLICK]

DRAM chip temperature, [CLICK]

The time that an aggressor row stays active [CLICK]

and victim DRAM cell’s physical location [CLICK]

In this study, we test 272 real DRAM chips of DDR3 and DDR4 modules from four major manufacturers [CLICK]

Based on our analyses, we draw 6 key takeaway lessons from 16 novel observations. Among these, we highlight that [CLICK]

A RowHammer bit flip is more likely to occur [CLICK]

in a bounded range of temperature [CLICK]

if the aggressor row is active for longer time [CLICK]

And in certain physical regions of the DRAM module under attack [CLICK]

Based on our findings, we propose several improvements. We believe and hope that our novel observations will inspire and aid future work on crafting more effective attacks and designing more effective and efficient defense mechanisms [END]

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Future Research

The effect of aging

Preliminary data on�aging via �68-day of �hammering

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Min. Hammer Count to Induce Read Disturbance Bitflips�HC_first (before aging)

Aging can lead to read disturbance bitflips �at fewer hammers

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Preliminary Aging Analysis

Significant variation in read disturbance vulnerability�across DRAM rows
Key Idea: To dynamically adapt the aggressiveness of existing solutions to the victim row’s read disturbance vulnerability
Key Results:

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