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Linux on RISC-V

with Open Source Hardware

Drew Fustini (@pdp7)

<drew@beagleboard.org>

Open Source Summit Japan 2020

https://tinyurl.com/y6j8lfyz

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$ whoami

  • Open Source Hardware designer at OSH Park
    • PCB manufacturing service in the USA
    • <drew@oshpark.com> | twitter: @oshpark
  • Board of Directors, BeagleBoard.org Foundation
    • BeagleBone is a small open source hardware Linux computer
    • <drew@beagleboard.org>
  • Board of Directors, Open Source Hardware Association (OSHWA)
    • OSHW Certification Program: https://certification.oshwa.org/
  • RISC-V Ambassador for RISC-V International

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RISC-V (virtual) meetups around the world

Find many more at: https://riscv.org/local/

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Upcoming Events

  • RISC-V (Virtual) Summit 2020

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Upcoming Events

Hardware whose design is made publicly available so that anyone can study, modify, distribute, make, and sell the design or hardware based on that design

​

(source: Open Source Hardware (OSHW) Statement of Principles 1.0)

​

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Upcoming Events

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Linux on Open Source Hardware with Open Source chip design�Chaos Communication Congress (36c3), December 2019

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Instruction Set Architecture (ISA)

  • Interface between hardware and software
    • C++ program is compiled into instructions for a microprocessor (CPU) to execute.
  • How does compiler know what instructions the CPU understands?
    • This is defined by the Instruction Set Architecture
  • ISA is a standard
    • a set of rules that define the tasks the processor can perform
    • proprietary ISA’s like x86 and ARM require commercial licensing

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RISC-V: a Free and Open ISA

  • History
    • Started in 2010 by computer architecture researchers at UC Berkeley
    • Watch the Instruction Sets Want to be Free by Krste Asanovic
  • Why “RISC”?
    • RISC = Reduced Instruction Set Computer
  • Why “V”?
    • 5th RISC instruction set to come of out UC Berkeley
  • Why is it “Free and Open”?
    • Specifications licensed as Creative Commons Attribution 4.0 International

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What is different about RISC-V?

  • Simple, clean-slate design
    • Far smaller than other commercial ISAs
    • Clear separation between unprivileged and privileged ISA
    • Avoids micro-architecture or technology dependent features
  • Modular ISA designed for extensibility and specialization
    • Small standard base, with multiple standard extensions
    • Suitable for everything from tiny microcontrollers to supercomputers
  • Stable
    • Base and standard extensions are frozen
    • Additions via optional extensions, not new versions of base ISA

(source: Instruction Sets Want to be Free (Krste Asanović))

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RISC-V Base Integer ISA

​

  • RV32I: 32-bit
    • less than 50 instructions needed!
  • RV32E: 32-bit embedded
    • reduces register count from 32 to 16 for tiny microcontrollers
  • RV64I: 64-bit
  • RV128I: 128-bit
    • Future-proof for nonvolatile RAM capacity; benefits security research

​

​

(source: RISC-V Summit 2019: State of the Union)

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RISC-V Standard Extensions

  • M: integer multiply/divide
  • A: atomic memory operations
  • F, D, Q: floating point, double-precision, quad-precision
  • G: “general purpose” ISA, equivalent to IMAFD
  • C: compressed instructions conserve memory and cache like ARM Thumb
  • Standard extensions have been ratified and will be supported forever
  • Linux distros like Debian and Fedora target RV64GC

​

​

(source: RISC-V Summit 2019: State of the Union)

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(source: Hot Chips Tutorial, Part 1: RISC-V overview and ISA design, Krste Asanovic)

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Learn more about RISC-V

  • Get up-to-speed quick with the RISC-V Reader

riscvbook.com

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RISC-V and Industry

  • RISC-V International now controls the specifications: riscv.org
    • Non-profit organization with 690+ members from 50 countries including companies, universities and more
    • Become a member (free of cost to individuals and non-profits)
    • YouTube channel has hundreds of talks!
  • Companies plan to ship billions of devices with RISC-V cores
    • Nvidia already shipping RISC-V cores for system management in its GPU products
    • Western Digital will be using RISC-V controllers in all of its storage products

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RISC-V and Industry

  • Avoid ISA licensing and royalty fees
    • including the legal costs and long delays due to complex licensing agreements
  • Freedom to choose micro-architecture implementation
    • only a few companies like Apple, Samsung and Qualcomm have ARM architecture licenses which allows them to do a custom implementation
  • Freedom to leverage existing open source implementations
    • including Linux-capable cores: Rocket & BOOM by Berkeley, Ariane by ETH Zurich PULP
  • Already has a well supported software ecosystem

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RISC-V around the world

  • RISC-V International based in Switzerland
    • U.S.-based RISC-V Foundation reincorporated at the beginning of 2020 as RISC-V International in Switzerland to avoid being hampered by U.S. politics
  • EU, India and Pakistan have RISC-V processor design initiatives
    • Desire for sovereign control of technology and avoid backdoors from other nations
  • Strong interest from chipmakers in China
    • U.S. companies banned in 2019 from doing business with Huawei… who’s next?
    • ARM was deemed to be a UK-origin technology in 2019, so it is ok to do business with Huawe but how long will that last? Will the Nvidia acquisition impact that?

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“Is RISC-V an Open Source processor?”

  • RISC-V is a set of specifications under an open source license

​

  • RISC-V implementations can be open source or proprietary

​

  • Open specifications make open source implementations possible
    • An open ISA like RISC-V enables the open source processor implementations

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RISC-V Privileged Architecture

  • Three privilege modes
    • User (U-Mode): applications
    • Supervisor (S-Mode): OS kernel
    • Machine (M-Mode): bootloader and firmware
  • Supported combinations of modes
    • M (simple embedded systems)
    • M, U (embedded systems with memory protection)
    • M, S, U (Unix-style operating systems with virtual memory)
  • Hypervisors run in modified S mode (HS)

​

​

(source: Co-developing RISC-V Hypervisor Support, Anup Patel)

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RISC-V Boot Flow

  • Follows commonly used multiple boot stages model
    • ZSBL and FSBL are initial platform-specific bootloaders (SiFive FU540 SoC in this example)
    • U-Boot is the final stage bootloader that jumps into Linux kernel
    • NOTE: hart is a hardware thread of execution, which users may refer to as a “core”

​

(source: RISC-V software ecosystem in 2020, Atish Patra)

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What is SBI?

  • SBI stands for Supervisor Binary Interface
    • calling convention between Supervisor (S-mode OS) and Supervisor Execution Environment (SEE)
    • allows supervisor-mode software to be written that is portable to all RISC-V implementations
  • Unix-class Platform Spec working group
    • Chaired by Al Stone
    • Now named the RISC-V Profiles and Platform Spec WG

(source: OpenSBI Deep Dive, Anup Patel)

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What is OpenSBI?

  • OpenSBI is an open source SBI implementation
    • avoid fragmentation of SBI implementations
  • Layers of implementation
    • Platform specific reference firmware
    • Platform specific library
    • SBI library
  • Provides run-time in M-mode
    • Typically used in boot stage following ROM/Loader
    • Provides support for reference platforms
    • Generic simple drivers included for M-mode to operate

(source: OpenSBI Deep Dive, Anup Patel)

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UEFI Support

(source: Introduction to RISC-V Boot Flow, Atish Patra and Anup Patel)

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RISC-V emulation in QEMU

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  • Support for RISC-V in mainline QEMU
    • QEMU can boot 32-bit and 64-bit mainline Linux kernel
    • QEMU can run OpenSBI, U-Boot and Coreboot
    • Draft versions of Hypervisor and Vector extensions supported
    • QEMU sifive_u machine can boot same binaries as the physical board
  • Tutorial: Running 64- and 32-bit RISC-V Linux on QEMU

(source: OpenSBI Deep Dive, Anup Patel)

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RISC-V in the Linux kernel

  • Initial port by Palmer Dabbelt landed in Linux 4.15
  • “What's missing in RISC-V Linux, and how YOU can help!”
    • Björn Töpel at Munich RISC-V meetup (jump to 43:25)
    • “A great way to learn the nitty gritty details of the Linux kernel”
    • “It’s a fun, friendly, and still pretty small community”

(source: “What's missing in RISC-V Linux, and how YOU can help!”, Björn Töpel)

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RISC-V in the Linux kernel

(source: “What's missing in RISC-V Linux, and how YOU can help!”, Björn Töpel)

$ ./Documentation/features/list-arch.sh riscv | grep TODO�� core/ cBPF-JIT : TODO | HAVE_CBPF_JIT # arch supports cBPF JIT optimizations� debug/ kprobes : TODO | HAVE_KPROBES # arch supports live patched kernel probe� debug/ kprobes-on-ftrace : TODO | HAVE_KPROBES_ON_FTRACE # arch supports combined kprobes and ftrace live patching� debug/ kretprobes : TODO | HAVE_KRETPROBES # arch supports kernel function-return probes� debug/ optprobes : TODO | HAVE_OPTPROBES # arch supports live patched optprobes� debug/ uprobes : TODO | ARCH_SUPPORTS_UPROBES # arch supports live patched user probes� debug/ user-ret-profiler : TODO | HAVE_USER_RETURN_NOTIFIER # arch supports user-space return from system call profiler� locking/ cmpxchg-local : TODO | HAVE_CMPXCHG_LOCAL # arch supports the this_cpu_cmpxchg() API� locking/ queued-rwlocks : TODO | ARCH_USE_QUEUED_RWLOCKS # arch supports queued rwlocks� locking/ queued-spinlocks : TODO | ARCH_USE_QUEUED_SPINLOCKS # arch supports queued spinlocks� perf/ kprobes-event : TODO | HAVE_REGS_AND_STACK_ACCESS_API # arch supports kprobes with perf events� sched/ membarrier-sync-core : TODO | ARCH_HAS_MEMBARRIER_SYNC_CORE # arch supports core serializing membarrier� sched/ numa-balancing : TODO | ARCH_SUPPORTS_NUMA_BALANCING # arch supports NUMA balancing� time/ arch-tick-broadcast : TODO | ARCH_HAS_TICK_BROADCAST # arch provides tick_broadcast()� time/ irq-time-acct : TODO | HAVE_IRQ_TIME_ACCOUNTING # arch supports precise IRQ time accounting� time/ virt-cpuacct : TODO | HAVE_VIRT_CPU_ACCOUNTING # arch supports precise virtual CPU time accounting� vm/ ELF-ASLR : TODO | ARCH_HAS_ELF_RANDOMIZE # arch randomizes the stack, heap and binary images of ELF binaries� vm/ huge-vmap : TODO | HAVE_ARCH_HUGE_VMAP # arch supports the ioremap_pud_enabled() and ioremap_pmd_enabled()� vm/ ioremap_prot : TODO | HAVE_IOREMAP_PROT # arch has ioremap_prot()� vm/ PG_uncached : TODO | ARCH_USES_PG_UNCACHED # arch supports the PG_uncached page flag� vm/ THP : TODO | HAVE_ARCH_TRANSPARENT_HUGEPAGE # arch supports transparent hugepages� vm/ batch-unmap-tlb-flush: TODO | ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH # arch supports deferral of TLB flush until multiple pages are unmapped

​

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RISC-V in the Linux kernel

(source: “What's missing in RISC-V Linux, and how YOU can help!” (Björn Töpel) and linux-riscv mailing list)

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RISC-V in the Linux kernel

(source: “What's missing in RISC-V Linux, and how YOU can help!” (Björn Töpel) and linux-riscv mailing list)

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Linux distro: Fedora

  • ”This project, informally called Fedora/RISC-V, aims to provide a complete Fedora experience on the RISC-V (RV64GC)”

(source: Fedora on RISC-V, Wei Fu)

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Linux distro: Fedora

  • QEMU and libvirt/QEMU
    • Fedora Images can run on the QEMU with graphics parameters (VGA and bochs-display).
  • SiFive Unleashed board
    • Fedora GNOME Image can run on SiFive Unleashed with Expansion Board, PCI-E graphic Card & SATA SSD
  • Installation instructions

​

(source: Fedora on RISC-V, Wei Fu)

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Linux distro: Debian

  • Port of Debian for the RISC-V architecture called riscv64
    • “a port in Debian terminology means to provide the software normally available in the Debian archive (over 20,000 source packages) ready to install and run”
  • 95% of packages are built for RISC-V
    • The Debian port uses RV64GC as the hardware baseline and the lp64d ABI (the default ABI for RV64G systems).

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OpenEmbedded / Yocto

  • meta-riscv: general hardware-specific BSP overlay for the RISC-V
    • The core BSP part of meta-riscv should work with different OpenEmbedded/Yocto distributions and layer stacks
    • Supports QEMU and the SiFive HiFive Unleashed board

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BuildRoot

  • RISC-V port is now supported in the upstream BuildRoot project
  • “Embedded Linux from scratch in 40 minutes (on RISC-V)”
    • Tutorial by Michael Opdenacker, Bootlin
    • Hardware emulator: QEMU
    • Cross-compiling toolchain: Buildroot
    • Bootloader: BBL Berkeley Boot Loader
    • Kernel: Linux 5.4-rc7
    • Root filesystem and application: BusyBox
    • That’s easy to compile and assemble in less than 40 minutes!

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SiFive Freedom FU540 SoC

  • SiFive is a start-up founded by members of the Berkeley RISC-V team
  • FU540 debuted in 2018 as the first RISC-V SoC that could run Linux
    • 4x U54 cores (up to 1.5 GHz) which �implement RV64GC to run Linux
    • 1x E51 low-power “minion” core for �system management tasks
    • 64-bit DDR4 with ECC
    • Gigabit Ethernet, ChipLink, SPI, I2C,�UART, GPIO, PWM (no USB)

​

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SiFive Freedom Unleashed

  • The first Linux-capable RISC-V dev board
    • And the board design is Open Source Hardware!
  • High performance compared to FPGA
    • FU540 SoC clocked over 10x faster than FPGA ‘soft’ cores
  • Too expensive for widespread adoption
    • Sold for $999 on CrowdSupply and no longer available
    • FU540 SoC chip is not sold separately
    • SiFive core business is designing cores, not SoC’s or boards

​

NOTE: ASIC is a term often used to indicate that an SoC (System-on-Chip) has a “hard” processor core constructed by silicon fab instead of “soft” core in an FPGA

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SiFive Freedom Unleashed

  • Fedora GNOME image running on Unleashed with PCIe graphics card

​

​

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Microchip PolarFire SoC

  • Microchip designed a SoC similar �to SiFive U540 but adds a FPGA
    • 4x 667 MHz U54 cores, 1x E51 core
    • PolarFire FPGA fabric with �25k to 460k logic elements (LEs)
    • DDR3/4, LPDDR3/4
    • PCIe Gen2, USB 2.0 OTG, 2x GbE
  • Full commercial product family
    • Available from distributors
    • Formerly branded as Microsemi�before Microchip acquired it

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Microchip Icicle board

  • PolarFire SoC dev board
    • $499 on CrowdSuppy
    • Pre-orders now shipping
    • Available soon from distributors
  • MPFS250T-FCVG484EES
    • 600 MHz clock RISC-V cores
    • 254K logic element FPGA
  • Memory
    • 2 GB LPDDR4 x 32
    • 8 GB eMMC flash and SD card

​

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SAVVY-V board

​

  • PolarFire SoC with physical stacking for clusters
    • 4 GB LPDDR4 RAM
    • 32 GB eMMC storage
    • Dual 10Gbit SFP+ fiber Ethernet
    • Dual 1Gbit copper Ethernet
    • 6x USB Type-C carrying PCIe
    • Coming soon on CrowdSupply

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Kendryte K210

​

  • 400MHz dual core RV64GC
    • 8MB SRAM but no DRAM interface
  • Affordable Sipeed dev boards
    • Sipeed MAiX BiT is only $13
  • Full support added in Linux 5.8
    • “RISC-V NOMMU and M-mode Linux”
    • Damien Le Moal, Christoph Hellwig
  • 2 boards supported by u-boot
    • Sean Anderson

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Kendryte K210

​

  • Buildroot with busybox for rootfs
    • upstreaming in progress on the mailing list
    • tutorial from CNX Software
  • 8MB runs out very quick!
    • MMU based on draft spec not supported by Linux
    • userspace needs shared library support
    • "RISC-V FDPIC/NOMMU toolchain/runtime support" (Maciej W. Rozycki)

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Kendryte�K210

​

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PicoRio

  • Open source project from RIOS Lab
    • Goal is to create low-cost Linux-capable RISC-V platform
  • Introduction by Zhangxi Tan
    • during RISC-V Global Summit back in September
    • Three phases of PicoRio planned
    • Samples of PicoRio 1.0 expected in Q4 2020

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SiFive Unmatched

​

  • Announced in October 2020
    • $665 on CrowdSupply
    • scheduled to ship in January 2021
  • SiFive Freedom FU740 SoC
    • 4x U74 RV64GC application cores
    • 1x S7 RV64IMAC embedded core

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SiFive Unmatched

​

  • Mini-ITX PC form factor
    • 8GB DDR4 RAM
    • 4x USB 3.2 Gen 1 ports
    • Gigabit Ethernet
    • x16 PCIe Gen 3 Expansion Slot
    • M.2 connector for NVMe SSD
    • M.2 connector for WiFi/Bluetooth

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Alibaba XuanTie 910

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  • T-Head is a subsidiary of Alibaba
  • 16-core 2.5 GHz RISC-V processor
    • implementation of draft Vector extension
    • expected to debut in 2021

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Sipeed board with Allwinner SoC

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  • Alibaba T-Head XuanTie C906
    • single-core RV64GCV processor up to 1 GHz
  • $12.50 per Sipeed tweet
    • At least 256 MB RAM
    • Planned to early 2021

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Open source FPGA toolchains

“RISC-V and FPGAs: Open Source Hardware Hacking”�Keynote at Hackday Supercon 2019 by Dr. Megan Wachs

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Open source FPGA toolchains

  • Project IceStorm for Lattice iCE40 FPGA

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Open source FPGA toolchains

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Open source FPGA toolchains

  • Project X-Ray & SymbiFlow for much more capable Xilinix Series 7
    • “Xilinx Series 7 FPGAs Now Have a Fully Open Source Toolchain!” [almost] Tim Ansell
    • “Open Source Verilog-to-Bitstream FPGA synthesis flow, currently targeting Xilinx 7-Series, Lattice iCE40 and Lattice ECP5 FPGAs. Think of it as the GCC of FPGAs”

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Hackaday Supercon badge

  • RISC-V “soft” core on ECP5 FPGA
  • Gigantic FPGA In Game Boy Form Factor

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“Team Linux on Badge”

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“Team Linux on Badge”

  • Jacob Creedon designed a cartridge board that adds 32MB of SDRAM to the Hackaday Supercon badge… before the event!

​

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source: https://twitter.com/ico_TC/status/1205996588499210241

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Why design an SoC in Python?

  • Python has advantages over traditional HDL like VHDL and Verilog
    • Many people already are familiar with Python than HDL (hardware description languages)
    • There are currently more software developers than hardware designers
  • Migen is a Python framework that can automate chip design
    • Leverages the object-oriented, modular nature of Python
    • Produces Verilog code so it can be used with existing chip design workflows
  • “Using Python for creating hardware to record FOSS conferences!”

​

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source: https://github.com/litex-hub/fpga_101�

​

​

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LiteX

  • Based on Migen, builds full SoC that can be loaded into an FPGA

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LiteX

  • “LiteX vs. Vivado: First Impressions”
  • Collection of open cores for DRAM, Ethernet, PCIe, SATA and more...

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Linux on LiteX-VexRiscv

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  • VexRiscv: 32-bit Linux-capable RISC-V core
    • Designed to be FPGA friendly
    • Written in Spinal HDL (based on Scala)
  • Builds an SoC using VexRiscv core and LiteX modules
    • Such as LiteDRAM, LiteEth, LiteSDCard, LitePCIe
    • “This project demonstrates how high level HDLs (Spinal HDL, Migen) enable new possibilities and complement each other. Results shown here are the results of a productive collaboration between open-source communities”
  • Supports large number of FPGA dev boards

​

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LiteX

  • upstream support for Hackaday Supercon badge:
  • https://github.com/litex-hub/litex-boards/pull/31

​

​

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https://twitter.com/GregDavill/status/1231082623633543168�

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Open Source ECP5 FPGA boards

  • Radiona.org ULX3S
    • 32MB SDRAM; ESP32 on board for WiFi and Bluetooth
    • Sold for $115 on CrowdSupply and Mouser

​

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Open Source ECP5 FPGA boards

  • OrangeCrab by Greg Davill
    • 128MB DDR RAM; Adafruit Feather form factor
    • Sold on GroupGets for $129

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Want to learn FPGAs? Try Fomu!

  • Online workshop from Tim Ansell and Sean Cross
  • $50 on CrowdSupply
  • Fits inside USB port!
  • Learn how to use:
    • MicroPython
    • Verilog
    • LiteX

​

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No hardware? Try Renode!

  • Renode can simulate physical hardware systems including CPU, peripherals, sensors, and wired or wireless network between nodes

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source: Renode supported boards

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source: Renode supported boards

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Trustworthy self-hosted computer

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source: “Toward a Trustable, Self-Hosting Computer System”�

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Linux on RISC-V

with Open Source Hardware

Drew Fustini (@pdp7)

<drew@beagleboard.org>

Open Source Summit Japan 2020

https://tinyurl.com/y6j8lfyz