1 of 31

Introduction to Verilog -21EC32

2 of 31

Syllabus

Module 4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of Description.

(Section 1.1 to 1.6.2, 1.6.4 (only Verilog), 2 of Text 3)

Verilog Data flow description: Highlights of Data flow description, Structure of Data flow description.

(Section 2.1 to 2.2 (only Verilog) of Text 3)

Module 4

2

11/5/2022

3 of 31

Text Books

3

11/5/2022

4 of 31

HDL

Hardware Description Language.

Specialized computer language like C to describe the structure and behaviour of digital logic systems.

Digital systems realized using FPGA and ASIC using HDL.

Two popularly used HDLs in both academia and industry alike : Verilog and VHDL

Module 2

4

11/5/2022

5 of 31

Module 2

5

11/5/2022

Code structure based on C language.

Case sensitive language unlike VHDL.

Used to design hardware and to verify the behavior of a piece of hardware.

Can be used to design digital circuits like encoders, multiplexers , counters, flip flop or even microprocessor.

Inevitable tool for Design Engineers and Verification Engineers.

VERILOG

6 of 31

Module 2

6

11/5/2022

1. Structure of Verilog module

a. Declaration

Name of the module

Inputs

Outputs

b. Body

Shows relationship between input and output ports.

c. End of module

7 of 31

Module 2

7

11/5/2022

Example 1 : Half adder

Task 1:

Write truth table of half adder.

Assume a and b as inputs, find the expression for sum and carry using K-map.

8 of 31

Module 2

8

11/5/2022

Verilog structure:

module half_adder (a, b, sum, carry);

input a;

input b;

output sum;

output carry;

assign sum = a ^ b;

assign carry = a & b;

endmodule

9 of 31

Module 2

9

11/5/2022

Assignment :

Qstn 1:

Write Verilog code for full adder.

10 of 31

Module 2

10

11/5/2022

Verilog ports:

input :

Must appear only on RHS of statement.
Port is read.

output :

Can appear on either side of assignment statement.

3. inout:

Can be used as both input and output.
Represents bidirectional bus.

11 of 31

Module 2

11

11/5/2022

2. Operators:

Used to perform various functions.

Logical operators

Perform logical operations like AND, OR and XOR.

a)i) Bitwise logical operators:

operate on corresponding bits of two operands.

Operand type: Bit, Result type: Bit

AND (&)
OR (|)
NAND ~(&)
NOR ~(|)
XOR ^
XNOR ~^
NOT ~

Task 2:

If X = 1001 and Y = 0111, find Z = X ^ Y.

12 of 31

Module 2

12

11/5/2022

a)ii) Boolean logical operators:

operate on two operands.
Result is Boolean, 0 (false), or 1 (true)

Boolean logical AND (&&)

Boolean logical OR (||)

Task 3:

If X = 1011 and Y = 0001, find X>1001 && X>Y

a)iii) Reduction operators:

operate on single operand.
Result is Boolean, 0 (false), or 1 (true)

Task 4:

If X = 1010, find Y = &X, where & is the Reduction AND operator.

Y= (Bit 3 & Bit 2 & Bit 1 & Bit 0)

13 of 31

Module 2

13

11/5/2022

b. Relational operators

To compare values of two objects.
Result: Boolean (true or false or don’t care)

Equality (==)
Inequality (!=)
Less than (<)
Less than or equal (<=)
Greater than (>)
Greater than or equal (>=)

Task 5:

If X = 1010 and Y = 10, evaluate X <= Y.

14 of 31

Module 2

14

11/5/2022

c. Arithmetic operators

Y : = (A + B) calculates Y as the sum of A and B.

Addition (A+B)
Subtraction (A-B)
Multiplication (A*B)
Division (A/B)
Modulus ( A%B)
Exponent (A ** B)
Concatenation {A, B}

Task 6:

If A = 1010 and B = 0011, evaluate A % B.

15 of 31

Module 2

15

11/5/2022

d. Shift and Rotate operators

Unary operators operating on a single operand.

Example if operand Y is 1110,

Y << 1 = 110x

(shift X one position left logical)

Task 7:

Find Y << 2

Y >> 1

Y >> 2

16 of 31

Module 2

16

11/5/2022

3. Datatypes

Refers to the type of operands or data used.

Example: type of signal can be bit (0 or 1)

Other datatypes : nets, registers, vectors, integer, real, parameters, arrays.

a. Nets

Predefined word: wire, e.g. wire S1 = 1’b0 declares a net by the name S1 whose initial value is 1’b0 ( 1 bit with value 0)

Values change continuously by the circuits that are driving them.

Value	Definition
0	false
1	true
x	unknown
z	high impedance

17 of 31

Module 2

17

11/5/2022

b. Registers

Used to store or remember values until they are updated.

Predefined word: reg

Ex: reg sum; (declares register by the name sum to store values until they are updated.

c. Vectors

Multiple bits including register and net.

Ex: wire [2:0] a = 3’d7

(net a has 3 bits and its initial value is decimal 7.

18 of 31

Module 2

18

11/5/2022

d. Integers

Declared as

integer sum; (sum is declared as integer)

e. Real

Floating point numbers declared as

real mass; (mass is declared as real)

f. Parameters

represent global constants.

g. Arrays

Registers and integers can be written as arrays.

19 of 31

Module 2

19

11/5/2022

Eg: parameter M =3;

integer carry [0:M]

carry is an integer having 4 elements, each element is of integer datatype.

20 of 31

Module 2

20

11/5/2022

Styles of description

Behavioural

Structural

Data flow

21 of 31

Module 2

21

11/5/2022

Behavioural

Models the system as to how outputs behave with inputs.

Includes predefined word “ always” or “initial”.

Example:

module half_adder (a, b, sum, carry);

input a, b;

output sum, carry;

reg sum, carry;

always @ (a, b)

begin

# 10 sum = a ^ b; // after 10 ns

# 10 carry = a & b; // after 10 ns

end

endmodule

22 of 31

Module 2

22

11/5/2022

2. Structural

Models the system as components or gates.

Uses names of gates.

Example:

module half_adder (a, b, sum, carry);

input a, b;

output sum, carry;

xor x1 (sum, a, b);

and a1 (carry, a, b) ;

endmodule

23 of 31

Module 2

23

11/5/2022

3. Data-flow

Describes how system’s signals flow from inputs to outputs.

Boolean function of outputs are written.

Statements are concurrent (occur at same time, controlled by events)

Example:

module half_adder (a, b, sum, carry);

input a, b;

output sum, carry;

assign sum = a ^ b;

assign carry = a & b ;

endmodule

24 of 31

Module 2

24

11/5/2022

Verilog Data Flow Description

25 of 31

Module 2

25

11/5/2022

Highlights of Data-flow Description

Shows how signal flows from system inputs to outputs.

Signal flow shown by Boolean function of the output or logical structure of the system.

Signal assignment statements are concurrent.

At any signal time, all signal assignment statements that have an event are executed concurrently.

26 of 31

Module 2

26

11/5/2022

Structure of Data-flow Description

1. Signal declaration and assignment statements

Here Y1 and Y2 are intermediaries.

Y1 and Y2 declared as signals using predefined word “wire”.

wire Y1, Y2;

Here Y1 and Y2 are intermediaries with continuously changing values with changes in device driving it.

27 of 31

Module 2

27

11/5/2022

Signal assignment:

Used to assign value to a signal using predefined word “assign”.

Eg: assign sum <= a and b

Execution done in two phases:

Calculation:

At time T0, value of sum is calculated using current values of a and b.

This value is not yet assigned to sum.

Assignment:

Calculated value assigned to sum after a delay time.

Assign #10 sum = a & b // delay time of 10 ns

28 of 31

Module 2

28

11/5/2022

Concurrent Signal assignment:

When event occurs on more than 1 statement, all statements are executed concurrently or simultaneously.

Regardless of order in architecture.

Sequential Signal assignment:

Statements are executed one after the other.

29 of 31

Module 2

29

11/5/2022

Constant declaration and assignment:

Value is constant within the program segment where it is visible.

Declared by its type such as time or integer

Eg: time period; (period is a constant of type time)

To assign a value of 10 ns,

time period = 10; (10 simulation screen time units )

If no delay specified, any change in one event will be immediately reflected in output.

Delay time to signal assignment:

assign #10 sum = a ^ b ;

30 of 31

Module 2

30

11/5/2022

2 x 1 MUX

E’	SEL	Output
H	X	0
L	0	A
L	1	B

A

B

E’

S

Y

2 X 1 mux

Y = ES’A + ESB

31 of 31

Module 2

31

11/5/2022

Assignment

Qstn 2:

Write Verilog data flow code for:

2 X 1 MUX.

D latch.

2-bit magnitude comparator.