What’s Next for BoW in 2024
(Optical, IoT and Memory Interfaces)
Shahab Ardalan, VP Engineering & Co-Founder, Enosemi
Kevin Donnelly, VP Strategic Marketing, Eliyan
Kash Johal, CEO & Founder, YorChip
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Bunch of Wires (BoW) Key Features
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What’s Next for BoW – BoW 2.1
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Motivation to have Optical D2D Interface
[J. Campenhou, ISSCC 2022]
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Optical Chiplet
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Supporting Optical Chiplet using BoW
ASIC
ASIC
B
o
W
-
T
X
B
o
W
-
R
X
E
Q
O2
E
T
I
A
CK
D
E
2
O
E
Q
D
R
CK
D
Chiplet-A
Chiplet-B
0dB
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Asking for participation
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Motivation to use D2D Interfaces for Memory
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D2D Signaling Technology Types
BoW 1.0 and UCIe 1.1
BoW 2.0
Memory PHYs
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Two Example D2D Use Cases for Memory
1) D2D use case Example
2) D2Mem use case example
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Potential BoW 2.1 Spec Changes to Support Memory
Potential Spec Changes by Use Cases | 1) D2D �Logic-to-Logic | 2) D2Mem �Logic-to-Memory |
BoW PHY Changes | Possibly none �(asymmetric Read vs Write BW already allowed) | Yes (Ex: dynamic bidi) |
Link Layer Changes | Likely new interface profiles and possibly bus variants; possible Link Layer changes to support asymmetry | Likely new interface profiles for each new memory type |
Configuration Doc | Yes (per Protocol?) | Yes (per memory type) |
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Bunch of Wires addendum to support IOT
ESPECIALLY FOR IOT & SENSORS
NEED LOW COST
<20% AREA
NEED LOW POWER
4 LANES VS 32
SIMPLE DEVICE
NO PLL REQUIRED
FLEXIBILITY
RX & TX
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CLK Rates
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Benefits /Drawbacks of IOT proposal
Advantages | Drawbacks |
Half-Link's data buses are in close proximity to the centralized clock, optimizing synchronization and signal integrity. | |
A symmetrical design can enable more layout sharing between TX and RX PHYs. | |
Enables dual purpose TX and RX PHYs. | |
Enable flexible RX/TX PHY signaling scheme | |
Device setup is simplified – Just works once set | |
Reduces PLL requirement for Device | |
Reduces Power & Cost | |
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Conclusion
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