�Chapter-2�Basic Computer Organization And Design

• Instruction codes,
• Computer registers,
• Computer instructions,
• Timing and Control,
• Instruction cycle,
• Memory-Reference Instructions,
• Input-output and interrupt,
• Design of Basic computer,
• Design of Accumulator Unit.

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Instruction Codes

• The organization of a computer is defined by its internal Registers, the timing and Control structure, and the set of instructions that it uses. the sequence of micro operations it performs on data stored in its register.
• The Internal Organization of a Digital System is defined by the Sequence of Micro operations it performs on data stored in its registers.
• A user of a Computer can Control the Process by means of a Program.

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• A Program is a Set of instructions that specifies the Operations, Operands and the sequence by which processing has to occur.
• A Computer instruction is a Binary code that specifies a sequence of microperations for the computer.
• The Computer Reads Each Instruction From Memory and Places it in a Control Register.
• The control then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of microoperations. Every computer has its own unique instruction set.

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• An instruction code is a group of bits that instruct the computer to perform a specific operation. It is usually divided into parts, each having its own particular interpretation. The most basic part of an instruction code is its operation part.
• The operation code of an instruction is a group of bits that define such operations as add, subtract, multiply, shift, and complement.
• The number of bits required for the operation code of an instruction depends on the total number of operations available in the computer. The operation code must consist of at least n bits for a given 2ⁿ (or less) distinct operations.

• As an illustration, consider a computer with 64 distinct operations, one of them being an ADD operation. The operation code consists of six bits, with a bit configuration 110010 assigned to the ADD operation . When this operation code is decoded in the control unit, the computer issues control signals to read an operand from memory and add the operand to a processor register.
• For every operation code, the control issues a sequence of microoperations needed for the hardware implementation of the specified operation. For this reason, an operation code is sometimes called a macrooperation because it specifies a set of microoperations.

• The operation part of an instruction code specifies the operation to be performed. This operation must be performed on some data stored in processor registers or in memory. An instruction code must therefore specify not only the operation but also the registers or the memory words where the operands are to be found, as well as the register or memory word where the result is to be stored.

• Memory words can be specified in instruction codes by their address. Processor registers can be specified by assigning to the instruction another binary code of k bits that specifies one of 2^k registers.
• There are many variations for arranging the binary code of instructions, and each computer has its own particular instruction code format.

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Stored Program Organization

• The simplest way to organize a computer is to have one processor register and an instruction code format with two parts.
• The first part specifies the operation to be performed and the second specifies an address.
• The memory address tells the control where to find an operand in memory.
• This operand is read from memory and used as the data to be operated on together with the data stored in the processor register.

Instructions are stored in one section of memory and data in another.

For a memory unit with 4096 words we need 12 bits to specify an address since 212 = 4096.

• If we store each instruction code in one 16-bit memory word, we have available 4 bits for the operation code (abbreviated opcode) to specify one out of 16 possible operations, and 12 bits to specify the address of an operand.
• The control reads a 16-bit instruction from the program portion of memory.
• It uses the 12-bit address part of the instruction to read a 16-bit operand from the data portion of memory.
• It then executes the operation specified by the operation code.
• Computers that have a single-processor register usually assign to it the name accumulator and label it AC.

• If an operation in an instruction code does not need an operand from memory, the rest of the bits in the instruction can be used for other purposes.
• For example, operations such as clear AC, complement AC, and increment AC operate on data stored in the AC register. They do not need an operand from memory. For these types of operations, the second part of the instruction code (bits 0 through 11 ) is not needed for specifying a memory address and can be used to specify other operations for the computer.

Indirect & Direct Address

• It is sometimes convenient to use the address bits of an instruction code not as an address but as the actual operand.
• When the second part of an instruction code specifies an operand, the instruction is said to have an immediate operand.
• When the second part specifies the address of an operand, the instruction is said to have a direct address.
• This is in contrast to a third possibility called indirect address.

• The I bit is 0, so the instruction is recognized as a direct address instruction. The opcode specifies an ADD instruction, and the address part is the binary equivalent of 457.The control finds the operand in memory at address 457 and adds it to the content of AC
• The instruction in address 35 shown in Fig. 5-2( c) has a mode bit I = 1. Therefore, it is recognized as an indirect address instruction. The address part is the binary equivalent of 300. The control goes to address 300 to find the address of the operand. The address of the operand in this case is 1350. The operand found in address 1350 is then added to the content of AC .
• The indirect address instruction needs two references to memory to fetch an operand. The first reference is needed to read the address of the operand; the second is for the operand itself. We define the effective address to be the address of the operand in a computation-type instruction or the target address in a branch-type instruction. Thus the effective address in the instruction of Fig. 5-2(b) is 457 and in the instruction of Fig 5-2( c) is 1350.

Computer Registers

• Computer instructions are normally stored in consecutive memory locations and are executed sequentially one at a time. The control reads an instruction from a specific address in memory and executes it. It then continues by reading the next instruction in sequence and executes it, and so on.
• This type of instruction sequencing needs a counter to calculate the address of the next instruction after execution of the current instruction is completed.
• It is also necessary to provide a register in the control unit for storing the instruction code after it is read from memory. The computer needs processor registers for manipulating data and a register for holding a memory address.

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• The memory unit has a capacity of 4096 words and each word contains 16 bits. 12 bits of an instruction word are needed to specify the address of an operand. This leaves three bits for the operation part of the instruction and a bit to specify a direct or indirect address.
• The data register (DR) holds the operand read from memory.
• The accumulator (AC) register is a general purpose processing register.
• The instruction read from memory is placed in the Instruction register (IR).
• The temporary register (TR) is used for holding temporary data during the processing.
• The memory address register (AR) has 12 bits since this is the width of a memory address.
• The program counter (PC) also has 12 bits and it holds the address of the next instruction to be read from memory after the current instruction is executed.

Program Counter

• The memory address register (AR) has 12 bits since this is the width of a memory address. The program counter (PC) also has 12 bits and it holds the address of the next instruction to be read from memory after the current instruction is executed. The PC goes through a counting sequence and causes the computer to read sequential instructions previously stored in memory.

• Instruction words are read and executed in sequence unless a branch instruction is encountered.
• A branch instruction calls for a transfer to a nonconsecutive instruction in the program.
• The address part of a branch instruction is transferred to PC to become the address of the next instruction.
• To read an instruction, the content of PC is taken as the address for memory and a memory read cycle is initiated.
• PC is then incremented by one, so it holds the address of the next instruction in sequence.

• Two registers are used for input and output.
• The input register (INPR) receives an 8-bit character from an input device.
• The output register (OUTR) holds an 8-bit character for an output device.

Basic computer registers and memory

Computer Bus System

• The basic computer has eight registers, a memory unit, and a control unit . Paths must be provided to transfer information from one register to another and between memory and registers.
• The number of wires will be excessive if connections are made between the outputs of each register and the inputs of the other registers. A more efficient scheme for transferring information in a system with many registers is to use a common bus.

• The outputs of seven registers and memory are connected to the common bus. The specific output that is selected for the bus lines at any given time is determined from the binary value of the selection variables S2S1S0.
• The number along each output shows the decimal equivalent of the required binary selection. For example, the number along the output of DR is 3. The 16-bit outputs of DR are placed on the bus lines when S2S1S0 = 011 since this is the binary value of decimal 3. The lines from the common bus are connected to the inputs of each register and the data inputs of the memory. The particular register whose LD (load) input is enabled receives the data from the bus during the next clock pulse transition. The memory receives the contents of the bus when its write input is activated. The memory places its 16-bit output onto the bus when the read input is activated and S2S1S0 = 1 1 1 .

• When the contents of AR or PC are applied to the 16-bit common bus, the four most significant bits are set to O's. When AR or PC receive information from the bus, only the 12 least significant bits are transferred into the register.

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• The input register INPR and the output register OUTR have 8 bits each and communicate with the eight least significant bits in the bus. INPR is connected to provide information to the bus but OUTR can only receive information from the bus. This is because INPR receives a character from an input device which is then transferred to AC . OUTR receives a character from AC and delivers it to an output device. There is no transfer from OUTR to any of the other registers.

Computer Instruction

• The basic computer has three instruction code formats, as shown in Figure Each format has 16 bits. The operation code (opcode) part of the instruction contains three bits and the meaning of the remaining 13 bits depends on the operation code encountered.
• A memory reference instruction uses 12 bits to specify an address and one bit to specify the addressing mode I. I is equal to 0 for direct address and to 1 for indirect address.

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• The register reference instructions are recognized by the operation code Ill with a 0 in the leftmost bit (bit 15) of the instruction. A register-reference instruction specifies an operation on or a test of the AC register. An operand from memory is not needed; therefore, the other 12 bits are used to specify the operation or test to be executed.
• Similarly, an input-output instruction does not need a reference to memory and is recognized by the operation code Ill with a 1 in the leftmost bit of the instruction. The remaining 12 bits are used to specify the type of input-output operation or test performed.

• The type of instruction is recognized by the computer control from the four bits in positions 12 through 15 of the instruction.
• If the three opcode bits in positions 12 though 14 are not equal to 111, the instruction is a memory-reference type and the bit in position 15 is taken as the addressing mode I.
• If the 3-bit opcode is equal to 111, control then inspects the bit in position 15. If this bit is 0, the instruction is a register-reference type.
• If the bit i s 1, the instruction is an input-Output Note that the bit in position 15 of the instruction code is designated by the symbol I but is not used as a mode bit when the operation code is equal to 1 1 1 .

Computer Instructions

• Only three bits of the instruction are used for the operation code. It may seem that the computer is restricted to a maximum of eight distinct operations.
• However, since register-reference and input-output instructions use the remaining 12 bits as part of the operation code, the total number of instructions can exceed eight . In fact, the total number of instructions chosen for the basic computer is equal to 25.

Basic Computer Instruction

* INSTRUCTION SET COMPLETENESS (4 Categories)

1. Arithmetic, logical, and shift instructions
2. Instructions for moving information to and from memory and processor registers
3. Program control instructions together with instructions that check statues conditions
4. Input and output instructions

Timing and Control

• The timing for all registers in the basic computer is controlled by a master clock generator.
• The clock pulses are applied to all flip-flops and registers in the system, including the flip-flops and registers in the control unit.
• The clock pulses do not change the state of a register unless the register is enabled by a control signal.
• The control signals are generated in the control unit and provide control inputs for the multiplexers in the common bus, control inputs in processor registers, and microoperations for the accumulator.

Two major types of control organization

• Hardwired control and micro programmed control.
• In the hardwired organization, the control logic is implemented with gates, flip-flops, decoders, and other digital circuits.
• It has the advantage that it can be optimized to produce a fast mode of operation.
• In the microprogrammed organization, the control information is stored in a control memory. The control memory is programmed to initiate the required sequence of microoperations.
• A hardwired control, as the name implies, requires changes in the wiring among the various components if the design has to be modified or changed.
• In the microprogrammed organization, the control information is stored in a control memory.

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Control unit basic computer

• The last three waveforms in Fig. 5-7 show how SC is cleared when D3T4 = 1 Output D3 from the operation decoder becomes active at the end of timing signal T2.
• When timing signal T4 becomes active, the output of the AND gate that implements the control function D3T4 becomes active. This signal is applied to the CLR input of SC. On the next positive clock transition (the one marked T, in the diagram) the counter is cleared to 0. This causes the timing signal To to become active instead of T5 that would have been active if SC were incremented instead of cleared.

Control Timing signals (Examples)

• To fully comprehend the operation of the computer, it is crucial that one understands the timing relationship between the clock transition and the timing signals. For example, the register transfer statement

T0: AR 🡨 PC

• specifies a transfer of the content of PC into AR if timing signal To is active. T0 is active during an entire clock cycle interval During this time the content of PC is placed onto the bus (with S2S1S0 = 010) and the LD (load) input of AR is enabled. The actual transfer does not occur until the end of the clock cycle when the clock goes through a positive transition. This same positive clock transition increments the sequence counter SC from 0000 to 0001 The next clock cycle has T1 active and T0 inactive.

INSTRUCTION CYCLE

• A program residing in the memory unit of the computer consists of a sequence of instructions.
• The program is executed in the computer by going through a cycle for each instruction. Each instruction cycle in turn is subdivided into a sequence of sub cycles or phases.

1. Fetch an instruction from memory.

2. Decode the instruction

3. Read the effective address from memory if the instruction has an indirect address.

4. Execute the instruction

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Fetch and Decode

• Initially, the program counter PC is loaded with the address of the first instruction
• The sequence counter SC is cleared to 0, providing a decoded timing signal T0. After each clock pulse, SC is incremented by one so that the timing signals go through a sequence T0, T1, T2, and so on.

T0: AR ← PC

T1: IR ← M[AR], PC ← PC + 1

T2: D0,…, D1 ← Decode IR (12-14), AR ← IR(0 −11), 1 ← IR (15)

• only AR is connected to the address inputs of memory, it is necessary to transfer the address from PC to AR during the clock transition associated with timing signal T0.
• The instruction read from memory is then placed in the instruction register IR with the clock transition associated with timing signal T1.
• At the same time, PC is incremented by one to prepare it for the address of the next instruction in the program.
• At time T2, the operation code in IR is decoded, the indirect bit is transferred to flip-flop I, and the address part of the instruction is transferred to AR. Note that SC is incremented after each clock pulse to produce the sequence T0, T1, and T2..

Register transfer for Fetch phase

• 1. Place the content of PC onto the bus by making the bus selection inputs S2S1S0 equal to 010.
• 2. Transfer the content of the bus to AR y enabling the LD input of AR. The next clock transition initiates the transfer form PC to AR since T0 = 1.

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T1: IR ← M[AR], PC ← PC + 1

• 1. Enable the read input of memory.
• 2. Place the content of memory onto the bus by making S2S1S0 = 111.
• 3. Transfer the content of the bus to IR by enabling the LD input of IR.
• 4. Increment PC by enabling the INR input of PC

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Register Reference Instruction

• Register-reference instructions are recognized by the control when D7 = 1 and I = 0.
• These instructions use bits 0 through 11 of the instruction code to specify one of 12 instructions. These 12 bits are available in IR(0-11). They were also transferred to AR during time T2.
• The control functions and microoperations for the register-reference instructions are. listed in Table 5-3. These instructions are executed with the clock transition associated with timing variable T3.
• Each control function needs the Boolean relation D7I’T3, which we designate for convenience by the symbol r . The control function is distinguished by one of the bits in IR(0-11). By assigning the symbol Bi, to bit i of IR, all control functions can be simply denoted by rB.
• For example, the instruction CLA has the hexadecimal code 7800 (see Table 5-2), which gives the binary equivalent 0111 1000 0000 0000.

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• Each control function needs the Boolean relation D7I ' T3, which we designate for convenience by the symbol r .
• The control function is distinguished by one o f the bits in IR(0-11). B y assigning the symbol B, to bit i of IR, all control functions can be simply denoted by rB;.
• For example, the instruction CLA has the hexadecimal code 7800 (see Table 5-2), which gives the binary equivalent 01 1 I 1000 0000 0000. The first bit is a zero and is equivalent to I ' . The next three bits constitute the operation code and are recognized from decoder output D7
• Bit 11 in IR is I and is recognized from 811 •
• The control function that initiates the rnicrooperation for this instruction is D7I ' T3 B11 = rB1 1 •
• The execution of a register-reference instruction is completed
• at time T3• The sequence counter SC is cleared to 0 and the control goes back to fetch the next instruction with timing signal T0

Execution of Register-Reference Instruction

MEMORY-REFERENCE INSTRUCTIONS

• AND to AC

D0T4 : DR ← M[AR]

D0T5: AC ← AC Λ DR, SC ← 0

The control function for this instruction uses the operation decoder D0 since this output of the decoder is active when the instruction has an AND operation whose binary code value is 000.

Two timing signals are needed to execute the instruction. The clock transition associated with timing signal T4 transfers the operand from memory into DR.

The clock transition associated with the next timing signal T5 transfers to AC the result of the AND logic operation between the contents of DR and AC.

The same clock transition clears SC to 0, transferring control to timing signal T0 to start a new instruction cycle

• ADD to AC

D1T4: DR ← M[AR]

D1T5: AC ← AC + DR, E ← Cout, SC ← 0

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The instruction adds the content of the memory word specified by the effective address to the value of AC.

The sum is transferred into AC and the output carry Cout is transferred to the E (extended accumulator) flip-flop.

• LDA : Load to AC :
• This instruction transfers the memory word specified by the effective address to AC.

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D2T4: DR ← M[AR]

D2T5: AC ← DR, SC ← 0

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The adder and logic circuit receive information from DR which can be transferred into AC. Therefore, it is necessary to read the memory word into DR first and then transfer the content of DR into AC

• STA : Store AC :
• This instruction stores the content of AC into the memory word specified by the effective address. Since the output of AC is applied to the bus and the data input of memory is connected to the bus,

D3T4: M[AR] ← AC, SC ← 0

BUN : Branch Unconditionally:

This instruction transfers the program to the instruction specified by the effective address.

The BUN instruction allows the programmer to specify an instruction out of sequence and we say that the program branches (or jumps) unconditionally.

D4T4: PC ← AR, SC ← 0

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• BSA : Branch and Save Return Address
• This instruction is useful for branching to a portion of the program called a subroutine or procedure. When executed, the BSA instruction stores the address of the next instruction in sequence (which is available in PC) into a memory location specified by the effective address.

M[AR] ← PC, PC ← AR + 1

M[135] ← 21, PC ← 135 + 1 = 136

D5T4: M[AR] ← PC, AR ← AR + 1

D5T5: PC ← AR, SC ← 0

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Example of BSA instruction execution

• ISZ : Increment and Skip if Zero
• This instruction increments the word specified by the effective address, and if the incremented value is equal to 0, PC is incremented by 1. The programmer usually stores a negative number (in 2’s complement) in the memory word.

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D6T4: DR ← M[AR]

D6T5: DR ← DR + 1

D6T6 : M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0

• ISZ : Increment and Skip if Zero
• This instruction increments the word specified by the effective address, and if the incremented value is equal to 0, PC is incremented by 1. The programmer usually stores a negative number (in 2’s complement) in the memory word.

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D6T4: DR ← M[AR]

D6T5: DR ← DR + 1

D6T6 : M[AR] ← DR, if (DR = 0) then (PC ← PC + 1), SC ← 0

Flowchart for memory-reference instructions

INPUT-OUTPUT AND INTERRUPT

• A computer can serve no useful purpose unless it communicates with the external environment.
• Instructions and data stored in memory must come from some input device. Computational results must be transmitted to the user through some output device.
• Commercial computers include many types of input and output devices.

INPUT-OUTPUT CONFIGURATION

Input Output Instructions

Program Interrupt

• The computer keeps checking the flag bit, and when it finds it set, it initiates an information transfer. The difference of information flow rate between the computer and that of the input-Output device makes this type of transfer inefficient. To see why this is inefficient, consider a computer that can go through an instruction cycle in 1 Micro Second. Assume that the input-Output device can transfer information at a maximum rate of 10 characters per second. This is equivalent to one character every 100,000MicroSecond. Two instructions are executed when the computer checks the flag bit and decides not to transfer the information.
• This means that at the maximum rate, the computer will check the flag 50,000 times between each transfer. The computer is wasting time while checking the flag instead of doing some other useful processing task.

• An alternative to the programmed controlled procedure is to let the external device inform the computer when it is ready for the transfer. In the meantime the computer can be busy with other tasks. This type of transfer uses the interrupt facility. While the computer is running a program, it does not check the flags.
• However, when a flag is set , the computer is momentarily interrupted from proceeding with the current program and is informed of the fact that a flag has been set. The computer deviates momentarily from what it is doing to take care of the input or output transfer. It then returns to the current program to continue what it was doing before the interrupt.

• The interrupt enable flip-flop lEN can be set and cleared with two instructions. When lEN is cleared to 0 (with the IOF instruction), the flags cannot interrupt the computer. When lEN is set to 1 (with the ION instruction), the computer can be interrupted. These two instructions provide the programmer with the capability of making a decision as to whether or not to use the interrupt facility.

Flow Chart for Interrupt Cycle

Demonstration of the interrupt cycle

Interrupt Cycle

• We are now ready to list the register transfer statements for the interrupt cycle. The interrupt cycle is initiated after the last execute phase if the interrupt flip-flop R is equal to 1. This flip-flop is set to 1 if lEN = 1 and either FGI or FGO are equal to 1.
• This can happen with any clock transition except when timing signals T0, T1 or T2 are active. The condition for setting flip-flop R to 1 can be expressed with the following register transfer statement:

• T0’T1’T2’(IEN)(FGI + FGO): R 🡨 1

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• The interrupt cycle is initiated after the last execute phase if the interrupt flip-flop R is equal to 1. This flip-flop is set to 1 if lEN = 1 and either FGI or FGO are equal to 1. This can happen with any clock transition except when timing signals T0, Tv or T2 are active. The condition for setting flip-flop R to 1 can be expressed with the following register transfer statement:

Modified fetch phase

• We now modify the fetch and decode phases of the instruction cycle. Instead of using only timing signals T0, T1 and T2 (as shown in Fig. 5-9) we will AND the three timing signals with R' so that the fetch and decode phases will be recognized from the three control functions R ' T0, R ' T1 and R ' T2•
• The reason for this is that after the instruction is executed and SC is cleared to 0, the control will go through a fetch phase only if R = 0. Otherwise, if R = 1, the control will go through an interrupt cycle. The interrupt cycle stores the return address (available in PC) into memory location 0, branches to memory location 1, and clears lEN, R, and SC to 0. This can be done with the following sequence of microoperations:

Design of Basic Computer

• The basic computer consists of the following hardware components:
• 1. A memory unit with 4096 words of 16 bits each
• 2. Nine registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC
• 3. Seven flip-flops: I, S , E, R, lEN, FGI, and FGO
• 4. Two decoders: a 3 x 8 operation decoder and a 4 x 16 timing decoder
• 5. A 16-bit common bus
• 6. Control logic gates
• 7. Adder and logic circuit connected to the input of AC

Design of Accumulator Logic

• The adder and logic circuit has three sets of inputs. One set of 16 inputs comes from the outputs of AC .
• Another set of 16 inputs comes from the data register DR .
• A third set of eight inputs comes from the input register INPR .
• The outputs of the adder and logic circuit provide the data inputs for the register.
• In addition, it is necessary to include logic gates for controlling the LD, INR, and CLR in the register and for controlling the operation of the adder and logic circuit.

Design of Accumulator Logic

Gate structure for controlling the LD, lNR, and CLR of AC.