1 of 59

Trigger and Electronics �in HEP experiments

Wen-Chen Chang

Institute of Physics, Academia Sinica

章文箴

中央研究院 物理研究所

2 of 59

Outline of Three Lectures

  • 12/14, Trigger, front-end-electronics and data acquisition system.
  • 12/21, Data-analysis technique and tools.
  • 12/28, Statistics for data analysis and physics interpretation.

3 of 59

Outline of �Trigger and Electronics

  • Event rate and luminosity.
  • DAQ: Data Acquisition System.
  • Trigger: what, why and how?
  • Electronics: ADC, TDC, Logical modules.

4 of 59

Accelerators

Accelerator

Time between collisions (ns)

Luminosity

(1030 cm-2s-1)

Energy (GeV)

CESR (CLEO)

4.2

2000

6

KEKB (Belle)

2

10,000

8 x 3.5

PEP-II (BaBar)

4.2

3,000

9 x 3.1

LEP (Aleph, Delphi, Opal, L3)

2200

50

101 (103??)

Accelerator

Time between collisions (ns)

Luminosity

(1030 cm-2s-1)

Energy (GeV)

HERA (H1, Zeus)

96

14

920 x 30

TeV (DØ, CDF)

396 (132)

200

2,000

LHC (Atlas, CMS)

25

10,000

14,000

e+e-

ep, pp, pp

Source: PDB’98

5 of 59

How to define a beam?

START                                                                       VETO

6 of 59

Structure of Beam Spill

Beam

7 of 59

Event Rate & Luminosity

8 of 59

Exercise

  • The total photo-production cross section γp for energy above 4 GeV is about 120μb (1 barn = 10-24cm2=100fm2).
  • Photon flux is about 106 Hz.
  • A liquid hydrogen target of length 11 cm: F= 2.1 b.
  • Luminosity= 106 /2.1 =0.48 μb-1 s-1
  • Event rate= 120*0.48=58 s-1

9 of 59

LabVIEW as an example

http://www.ni.com/aap/

10 of 59

Data Acquisition System (DAQ)

Trigger Detectors

Multiplexer

Triggered Devices

Buffer

Online Computer

Controlled Devices

Data Storage

Trigger

Logic

11 of 59

12 of 59

13 of 59

14 of 59

15 of 59

LHC Example

LHC design

~1 GHz input rate

~1 kHz W events

~10 Hz top events

<<< 1 Hz Higgs events

DAQ speed ~ 100 Hz

Level-1 Triggers

1 GHz 🡪 100 kHz

High Level Triggers

100 kHz 🡪 100 Hz

16 of 59

Definition and Need of Trigger

  • A trigger is an electronic signal indicating the occurrence of a desired temporal and spatial correlation in the detector signals:

B(beam) ⊗ F(final state in detector)

  • Goal:
    • Select rare events and suppress background events.
    • Reduce ‘dead time’ of data acquisition system by reducing the amount of data taking.
    • Reduce the cost of data storage and effort the data reduction.

17 of 59

Dead Time

  • Definition: the non-sensitive period of the detector or the electronics.
  • The loss of triggers caused by dead time must be corrected for and kept small for reasons of efficiency.
  • Dead time for detectors: nsec for scintillators and up to micro- and milliseconds for wire chambers.
  • Dead time for electronics: nsec for NIM modules and micro-sec for DSP.
  • Dead time for DAQ: order of msec.

18 of 59

Pipelines

  • The trigger needs finite time for its decision.
  • Trigger cannot cause deadtime during decision
  • To make dead timeless must have pipeline to store everything in FE
    • Switched Capacitor Arrays (SCAs)
    • DRAM
    • Shift Registers
    • Sample & Hold Shaping
    • Old fashion Delay Lines

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Data for BX #

Dec. for BX 1

Dec. for BX 2

Dec. for BX 3

Dec. for BX 4

Dec. for BX 5

Dec. for BX 6

Dec. for BX 7

Pipelined

Trigger

Trigger Output

19 of 59

History: Bubble Chambers

  • Bubble Chambers, Cloud Chambers, etc. (4π)
    • DAQ was a stereo photograph!
    • Low level trigger was the accelerator cycle
      • Each expansion was photographed
    • High level trigger was human (scanners).
    • No Trigger

20 of 59

Typical Designs

  • Required rejection is orders of magnitude
  • Cannot do it at beam crossing rate
    • Algorithms to attain required rejection are too sophisticated.
    • Accelerator backgrounds can also contribute to the problem
      • e+e- vs pp
  • Multi-Level trigger
    • Algorithms implemented in Hardware
      • Specialized, often matched to geometry of detector
    • Algorithms implemented in Software
      • Farm

Level 1

(HW)

Level 2+

(SW/HW)

Detector

Course Grained Readout

Full Resolution Readout

To Storage

DØ: 7MHz

DØ: 10kHz

DØ: 50Hz

Real Time

21 of 59

Data Flow

Data Link to Readout Buffers

Level-1 Triggers

Data Processing and Transfer

Level-2 Hardware Triggers

Event Building Switch

Level-3 Processor Farms

Data Archiving

Optical Technology

High Density FPGA, Custom ASIC (?)

Custom Electronics, Bus Speed

Trigger Primitive Processors

Gigabit Ethernet++, ATM

Operating System, Number of Nodes, Software

Tape Cost, Storage Technology, Ability to Analyze

22 of 59

Classification of �Higher-Level Triggers

  • Track multiplicity of the event
  • Direction of particles
  • Deflection or curvature of particles to measure momentum
  • Co-planarity of the event
  • Type of particle
  • Deposited energy
  • Missing energy
  • Invariant mass
  • Interaction point of event or secondary interaction

23 of 59

Trigger of Invariant Mass

24 of 59

Multi Level Trigger

  • Level 1 is hardware based
    • Identifies Jets, Tracks, Muons, Electrons
    • Operates on reduced or course detector data
  • Level 2 is often a composite
    • Hardware to preprocess data
      • Some Muon processors, Silicon Triggers
    • Software to combine
      • Matches, Jet finders, etc.
  • Level 3 is a PC farm
    • General Purpose CPUs

25 of 59

Electronic Modules� Level 1 Trigger

  • NIM (nuclear instrumental module) standard, operating at a speed of < 10 ns.
  • Discriminator
  • Coincidence register
  • Logical unit: AND/OR
  • Interrupt (gate) generator
  • Fan-in/Fan-out: linear and logic
  • Gate generator

http://www.lecroy.com/lrs/dsheets/dslib.htm

26 of 59

Discriminator and Coincidence

Discriminator

Coincidence

27 of 59

Trigger for Rutherford Scattering

28 of 59

Trigger for 2-body Scattering

29 of 59

Measurement of Muon Lifetime

30 of 59

What is a lifetime?

N = N0 e –t/τ

Our Detector

μ

ν

ν

e

By measuring the time difference muon entrance and the electron production, we can calculate the muon lifetime τ.

So we need a detector to count a double pulse.

31 of 59

For data analyses:

One can plot muon decay times and fit to

N = N0 e –t/τ + Nb

To find out the lifetime. Here one needs to be careful about the flat background.

32 of 59

Trigger for �Muon Lifetime Measurement

33 of 59

BELLE DAQ

34 of 59

Front-End-Electronics� in Data Acquisition

  • Electronic module:
    • ADC: analog-digital converter
    • TDC: time-digital converter
    • Latch
    • Memory
    • Interrupt generator
  • Bus system:
    • CAMAC
    • FASTBUS
    • VME
    • PCI

http://www.lecroy.com/lrs/dsheets/dslib.htm

35 of 59

TIME-TO-DIGITAL CONVERTER

  • Uses time-to-charge converters to supply Charge Multiplexers with charge proportional to the time between Common Start and Stops.
  • Measure the charge by high-resolution (12-bit) ADC.

36 of 59

ANALOG-TO-DIGITAL CONVERTER

  • the input to the ADC is sampled and the result is stored as charge on a capacitor. After a short interval, the capacitor is discharged at a constant rate, producing a time proportional to the input charge. The time is measured by counting the number of oscillator pulses during the discharge interval.

37 of 59

Lecroy 2249A CHARGE�ANALOG-TO-DIGITAL CONVERTER

  • Charge or Voltage Input
  • High Sensitivity, -0.25 pC or -1 mV
  • Wide Dynamic Range, 10 or 11 Bits
  • Excellent Linearity
  • Fast Conversion, 100 μsec
  • Fast Clear Input

38 of 59

Lecroy 1875A HIGH RESOLUTION TIME-TO-DIGITAL CONVERTER

  • High Sensitivity, to 25 psec/Count
  • Short Conversion Time, 10 µsec + 2.5 µsec Per Hit Channel
  • Fast Clear, 950 nsec
  • Multiple Event Buffer, 8 Events
  • Common Start Mode of Operation

39 of 59

CAMAC Crate

40 of 59

VME 6U & 9U

41 of 59

Backplane of VME

42 of 59

FASTBUS

43 of 59

Characteristics of Data Bus

44 of 59

SPring-8 Flash ADC

VME 9U, 32 channel, 40 MHz, 10 bits.

  • ADC
  • FPGA
  • FIFO

45 of 59

How much Data we receive?

  • 40 MHz sampling rate = 25 nsec
  • Strobe width = 10 micro-sec = 10,000 nsec
  • 10 bits
  • 100 channels
  • Total for one event = 10000/25*10*100 = 400 Kb = 50 KB
  • 50 Hz DAQ rate => 2.5 MB per sec =>150 MB per min =>9 GB per hour

46 of 59

Field Programmable Gate Array

  • Board on a chip
    • Revolutionized the way board design is done.
    • Logic design is not frozen when the board is laid out.
      • But much faster than running a program in microcode or a microprocessor.
    • Can add features at a later time by adding new logic equations.
    • Basically a chip of unwired logical gates (flip-flops, counters, registers, etc.).

Transistor

Logic Chip

Single Task

IC

Gate Array

Simple Programmable Logic Devices (SPLD)

Complex Programmable Logic Devices (CPLD)

Field Programmable Gate Arrays (FPGA)

Field Programmable InterConnect (FPIC)

47 of 59

Receiver & Driver

FADC

Receiver & Driver

FADC

Receiver & Driver

FADC

Receiver & Driver

FADC

CH 1

CH 4

CH 3

CH 2

10

10

10

10

Pre-Processing FPGA

Download EEPROM

Clock

Trigger

DSP

CPLD

Dual-port

RAM

FADC Block

x8

Download EEPROM

JTAG

Reset

Flag 4

VD[0..31]

Write

Write

CPU Read

CPU Read

Dual-port FIFO

VA[8..15]

VD[0..31]

VD[0..31]

VA[8..15]

DSP Read

DSP Read

VA[8..15]

CS

VD[0..31]

VME Bus

This design has the advantages as follows:

(1) Zero Dead time.

(2) Flexible algorithm can be installed into the DSP.

(3) User can select the functions.

(4) Divide each block into individual module without conflicting.

Operation of Flash ADC

48 of 59

The Control Flow of FADC

< 5 events

Send IRQ to VME CPU

DAQ READ FIFO

DAQ send Reset

FADC clear BUSY

Clear trigger Veto

Yes

No

DAQ Start

Trigger Count *Veto

NIM

CPLD FADC Trigger Clock 100MHz

Trigger signal

Trigger

FADC

BUSY

FADC Module

Preamplifier Module

For each channel

VME

CPU

Reset

Master

Slave

Trigger , Conversion

Clock

49 of 59

50 of 59

51 of 59

Reading Assignment

http://atlas.web.cern.ch/Atlas/GROUPS/DAQTRIG/daqtrig.html

52 of 59

References

  • Data Analysis Techniques for High-Energy Physics, R. Fruhwirth et al., Cambridge University Press 2000.
  • Introduction to Experimental Particle Physics, R. C. Fernow, Cambridge University Press 1986.
  • Techniques for Nuclear and Particle Physics Experiments, W.R. Leo, Springer-Verlag 1994.
  • Data Acquisition and Trigger Upgrades, Jamie Nagle, RHIC Detector Workshop 2001.
  • Triggering In High Energy Physics, Gordon Watts, Instr’ 99.

53 of 59

Coincidence

54 of 59

Colliders

55 of 59

Data Acquisition System

  • Data acquisition system (DAQ) is the process of gathering information in an automated fashion from analog and digital measurement sources such as sensors and devices under test. Data acquisition uses a combination of computer-based measurement hardware and software to provide a flexible, user-defined measurement system.
  • An environment for signal acquisition, measurement analysis, and data presentation.

56 of 59

Algorithms in Hardware

  • Cut out simple, high rate backgrounds
    • beam-gas (HERA)
      • z vertex
    • QCD (TeV)
      • jet energy, track matching
  • Capabilities are Limited
    • Feature Extraction from single detectors
      • Hadronic or EM Jets, tracks, muon stubs
    • Combined at Global Trigger
      • EM Object + Track
  • Characteristics:
    • High speed & Dead-timeless
    • Limited ability to modify algorithm
      • But thresholds typically can be modified
    • Algorithms Frequently Matched to the detector (and readout) geometry
      • Vertical Design
  • Built from Modern Components
    • Custom (ASICs)
    • Programmable Logic Arrays (FPGAs, etc.)

57 of 59

Algorithms in Software

  • Sophisticated Algorithms
    • Frequently separating background physics processes from the interesting processes.
    • Some experiments run their offline reconstruction online (Hera-B, CDF)
      • Perhaps 2D tracking instead of 3D tracking.
    • Data from more than one detector often used.
  • Two common implementations:
    • DSPs tend to live at lower levels of the trigger.
      • Stub finders in muon DØ’s muon system.
      • Transputers in ZEUS’ L2, DSPs on HERAB L2 & L3
    • CPU Farms tend to be at the upper end

58 of 59

Farm Triggers

  • Industry has revolutionized how we do farm processing
    • Wide scale adoption by HEP.
    • Online and Offline.
    • One CPU, one event
      • Not massively parallel
  • Data must be fed to farm
    • As many ways as experiments
    • Flow Management & Event Building
  • Farm Control
    • Distributed system can have 100’s of nodes that must be kept in sync.

DAQ &

HW Triggers

Trigger Farm

To Tape or Further

Triggering

59 of 59

NA48 Data Acquisition