Trigger and Electronics �in HEP experiments
Wen-Chen Chang
Institute of Physics, Academia Sinica
章文箴
中央研究院 物理研究所
Outline of Three Lectures
Outline of �Trigger and Electronics
Accelerators
Accelerator | Time between collisions (ns) | Luminosity (1030 cm-2s-1) | Energy (GeV) |
CESR (CLEO) | 4.2 | 2000 | 6 |
KEKB (Belle) | 2 | 10,000 | 8 x 3.5 |
PEP-II (BaBar) | 4.2 | 3,000 | 9 x 3.1 |
LEP (Aleph, Delphi, Opal, L3) | 2200 | 50 | 101 (103??) |
Accelerator | Time between collisions (ns) | Luminosity (1030 cm-2s-1) | Energy (GeV) |
HERA (H1, Zeus) | 96 | 14 | 920 x 30 |
TeV (DØ, CDF) | 396 (132) | 200 | 2,000 |
LHC (Atlas, CMS) | 25 | 10,000 | 14,000 |
e+e-
ep, pp, pp
Source: PDB’98
How to define a beam?
START VETO
Structure of Beam Spill
Beam
Event Rate & Luminosity
Exercise
LabVIEW as an example
http://www.ni.com/aap/
Data Acquisition System (DAQ)
Trigger Detectors
Multiplexer
Triggered Devices
Buffer
Online Computer
Controlled Devices
Data Storage
Trigger
Logic
LHC Example
LHC design
~1 GHz input rate
~1 kHz W events
~10 Hz top events
<<< 1 Hz Higgs events
DAQ speed ~ 100 Hz
Level-1 Triggers
1 GHz 🡪 100 kHz
High Level Triggers
100 kHz 🡪 100 Hz
Definition and Need of Trigger
B(beam) ⊗ F(final state in detector)
Dead Time
Pipelines
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data for BX #
Dec. for BX 1
Dec. for BX 2
Dec. for BX 3
Dec. for BX 4
Dec. for BX 5
Dec. for BX 6
Dec. for BX 7
Pipelined
Trigger
Trigger Output
History: Bubble Chambers
Typical Designs
Level 1
(HW)
Level 2+
(SW/HW)
Detector
Course Grained Readout
Full Resolution Readout
To Storage
DØ: 7MHz
DØ: 10kHz
DØ: 50Hz
Real Time
Data Flow
Data Link to Readout Buffers
Level-1 Triggers
Data Processing and Transfer
Level-2 Hardware Triggers
Event Building Switch
Level-3 Processor Farms
Data Archiving
Optical Technology
High Density FPGA, Custom ASIC (?)
Custom Electronics, Bus Speed
Trigger Primitive Processors
Gigabit Ethernet++, ATM
Operating System, Number of Nodes, Software
Tape Cost, Storage Technology, Ability to Analyze
Classification of �Higher-Level Triggers
Trigger of Invariant Mass
Multi Level Trigger
Electronic Modules� Level 1 Trigger
http://www.lecroy.com/lrs/dsheets/dslib.htm
Discriminator and Coincidence
Discriminator
Coincidence
Trigger for Rutherford Scattering
Trigger for 2-body Scattering
Measurement of Muon Lifetime
What is a lifetime?
N = N0 e –t/τ
Our Detector
μ
ν
ν
e
By measuring the time difference muon entrance and the electron production, we can calculate the muon lifetime τ.
So we need a detector to count a double pulse.
For data analyses:
One can plot muon decay times and fit to
N = N0 e –t/τ + Nb
To find out the lifetime. Here one needs to be careful about the flat background.
Trigger for �Muon Lifetime Measurement
BELLE DAQ
Front-End-Electronics� in Data Acquisition
http://www.lecroy.com/lrs/dsheets/dslib.htm
TIME-TO-DIGITAL CONVERTER
ANALOG-TO-DIGITAL CONVERTER
Lecroy 2249A CHARGE�ANALOG-TO-DIGITAL CONVERTER
Lecroy 1875A HIGH RESOLUTION TIME-TO-DIGITAL CONVERTER
CAMAC Crate
VME 6U & 9U
Backplane of VME
FASTBUS
Characteristics of Data Bus
SPring-8 Flash ADC
VME 9U, 32 channel, 40 MHz, 10 bits.
How much Data we receive?
Field Programmable Gate Array
Transistor
Logic Chip
Single Task
IC
Gate Array
Simple Programmable Logic Devices (SPLD)
Complex Programmable Logic Devices (CPLD)
Field Programmable Gate Arrays (FPGA)
Field Programmable InterConnect (FPIC)
Receiver & Driver
FADC
Receiver & Driver
FADC
Receiver & Driver
FADC
Receiver & Driver
FADC
CH 1
CH 4
CH 3
CH 2
10
10
10
10
Pre-Processing FPGA
Download EEPROM
Clock
Trigger
DSP
CPLD
Dual-port
RAM
FADC Block
x8
Download EEPROM
JTAG
Reset
Flag 4
VD[0..31]
Write
Write
CPU Read
CPU Read
Dual-port FIFO
VA[8..15]
VD[0..31]
VD[0..31]
VA[8..15]
DSP Read
DSP Read
VA[8..15]
CS
VD[0..31]
VME Bus
This design has the advantages as follows:
(1) Zero Dead time.
(2) Flexible algorithm can be installed into the DSP.
(3) User can select the functions.
(4) Divide each block into individual module without conflicting.
Operation of Flash ADC
The Control Flow of FADC
< 5 events
Send IRQ to VME CPU
DAQ READ FIFO
DAQ send Reset
FADC clear BUSY
Clear trigger Veto
Yes
No
DAQ Start
Trigger Count *Veto
NIM
CPLD FADC Trigger Clock 100MHz
Trigger signal
Trigger
FADC
BUSY
FADC Module
Preamplifier Module
For each channel
VME
CPU
Reset
Master
Slave
Trigger , Conversion
Clock
Reading Assignment
http://atlas.web.cern.ch/Atlas/GROUPS/DAQTRIG/daqtrig.html
References
Coincidence
Colliders
Data Acquisition System
Algorithms in Hardware
Algorithms in Software
Farm Triggers
DAQ &
HW Triggers
Trigger Farm
To Tape or Further
Triggering
NA48 Data Acquisition