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Module 5

VLSI Design – 18EC72

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Semiconductor Memories

(10.1 to 10.3 of Text 1)

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Outline

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  • Introduction
  • Dynamic Random Access Memory (DRAM)
  • Static Random Access Memory (SRAM)

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Introduction

  • What are Semiconductor memories ?
  • What are the key design criteria's to be considered while designing memories ?
  • What are the different types of memories ?

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Typical random-access memory array organization

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Read-only Memory( ROM circuits)

  • Example of a 4-bit x 4-bit NOR-based ROM array.

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Read-only Memory( ROM circuits)

  • Only one word line is activated (selected) at a time by raising its voltage to VDD, while all other rows are held at a low voltage level.
  • If an active transistor exists at the cross point of a column and the selected row, the column voltage is pulled down to the logic low level by that transistor.
  • If no active transistor exists at the cross point, the column voltage is pulled high by the pMOS load device.
  • Thus, a logic " 1 "-bit is stored as the absence of an active transistor, while a logic ""-bit is stored as the presence of an active transistor at the cross point.

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Layout example of a NOR ROM array.

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Layout of the 4-bit x 4-bit NOR ROM array

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A 4-bit x 4-bit NAND-based ROM array

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Row address decoder example for 2 address bits and 4 word lines.

  • Row decoder designed to drive a NOR ROM array must, by definition, select one of the 2 word lines by raising its voltage to VOH.
  • Figure shows Row address decoder example for 2 address bits and 4 word lines.

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NOR based �Row address decoder example for 2 address bits and 4 word lines.

  • A most straightforward implementation of this decoder is another NOR array, consisting of 4 rows (outputs) and 4 columns (two address bits and their complements).

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Implementation of the row decoder circuit and the ROM array as two adjacent NOR planes and NAND planes��

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Bit-line (column) decoder arrangement using a NOR address decoder and nMOS pass transistors for every bit line

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Bit-line (column) decoder arrangement using a NOR address decoder and nMOS pass transistors for every bit line

  • Only one nMOS pass transistor is turned on at a time, depending on the column address bits applied to the decoder inputs.
  • The conducting pass transistor routes the selected column signal to the data output. Similarly, a number of columns can be chosen at a time, and the selected columns can be routed to a parallel data output port.
  • Note that the number of transistors required for this column decoder implementation is 2(M+ 1), i.e., 2m pass transistors for each bit line and M 2 M transistors for the decoder circuit.

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Static Read-Write Memory (SRAM) Circuits

  • Read-write (R/W) memory circuits are designed to permit the modification (writing) of data bits to be stored in the memory array, as well as their retrieval (reading) on demand.
  • The memory circuit is said to be static if the stored data can be retained indefinitely (as long as a sufficient power supply voltage is provided), without any need for a periodic refresh operation.
  • The data storage cell, i.e., the 1-bit memory cell in static RAM arrays, invariably consists of a simple latch circuit with two stable operating points (states). Depending on the preserved state of the two-inverter latch circuit, the data being held in the memory cell.

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Various configurations of the static RAM cell.

  • Symbolic representation of the two-inverter latch circuit with access switches.

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Various configurations of the static RAM cell.

  • Generic circuit topology of the MOS static RAM cell

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Various configurations of the static RAM cell.

  • Resistive-load SRAM cell.

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Various configurations of the static RAM cell.

  • Depletion-load nMOS SRAM cell.

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Various configurations of the static RAM cell.

  • Full CMOS SRAM cell

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SRAM operation principles

  • Basic structure of the resistive-load SRAM cell, shown with the column pull-up transistors.

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SRAM operation principles

  • four-transistor resistive-load SRAM cell widely used in high-density memory arrays, consisting of a pair of cross-coupled inverters.
  • The two stable operating points of this basic latch circuit are used to store a one-bit piece of information; hence, this pair of cross-coupled inverters make up the central component of the SRAM cell.
  • To perform read and write operations, we use two nMOS pass transistors, both of which are driven by the row select signal, RS.
  • SRAM is accessed via two bit lines or columns, instead of one. This complementary column arrangement allows for a more reliable operation. When the word line (RS) is not selected, i.e., when the voltage level of line RS is equal to logic "0," the pass transistors M3 and M4 are turned off.

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SRAM operation principles

  • The simple latch circuit consisting of two cross-connected inverters preserves one of its two stable operating points; hence, data is being held. At this point, consider the two columns, C and C.
  • If all word lines in the SRAM array are inactive, the relatively large column capacitances are charged-up by the column pull-up transistors, MP1 and MP2. Since both transistors operate in saturation,
  • the steady-state voltage level Vc for both columns is determined by the following relationship:

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SRAM operation principles

  • Once the memory cell is selected, four basic operations may be performed on this cell

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SRAM operation principles

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Typical row and column voltage waveforms of the resistive-load SRAM during read and write

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Circuit topology of CMOS SRAM Cell�

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Fast Sense Amplifier

  • Differential current-mirror amplifier to speed up the memory read access time

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Testing and Verification

(15.1, 15.3, 15.5 15.6.1 to 15.6.3 of TEXT 2)

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Outline

  • Introduction
  • Logic Verification Principles
  • Manufacturing Test Principles
  • Design for Testability

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Testing

  • Testing is one of the most expensive parts of chips
    • Logic verification accounts for > 50% of design effort for many chips
    • Debug time after fabrication has enormous opportunity cost
    • Shipping defective parts can sink a company
  • Example: Intel FDIV bug (1994)
    • The processor had floating-point divide problem can be corrected by changing mask alignments
    • Recall cost $475 Million

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  • Does the chip simulate correctly?
    • Usually done at HDL level
    • Verification engineers write test bench for HDL
      • Can’t test all cases
      • Look for corner cases
  • Test the first chips back from fabrication
  • Logic bugs vs. electrical failures
    • Most chip failures are logic bugs from inadequate simulation
    • Some are electrical failures
      • Crosstalk, Dynamic nodes: leakage, charge sharing, Ratio failures
    • A few are tool or methodology failures (e.g. DRC)
  • Fix the bugs and fabricate a corrected chip

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Functional Equivalence of Various levels of Abstraction�

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Pointers for Debugging

  • Keep an annotated and dated logbook for all tests done.
  • When postulating a cause for the bug and a test, do one change at a time and observe the result: Changing many things and then seeing if they work will not logically lead you to the bug and is commonly called the “shotgun approach.”
  • Check everything two or three times; never assume anything unless it is measured and logged in a notebook. Have someone independently check critical measurements.
  • Check signals and supply voltages at the pins of the IC; frequently, new test boards have errors.
  • Double-check the specified chip I/O and perform a continuity check from the IC pins to expected places (i.e., test pins, supplies) on the board.

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Pointers for Debugging

  • Use freeze spray or a heat gun to cool down or heat up a circuit to check for temperature problems.
  • Check the state of any internal registers against that noted in the documentation.
  • Evaluate the timing of any inputs and outputs with respect to the clock; often setup or hold times can be violated in a new test setup.
  • When a bug is discovered and corrected, hunt for other portions of the design that might have a similar bug that hasn’t been detected yet. Where there is one rat, there are many rats! Never assume anything––question everything––a slight touch of paranoia helps!

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Logic Verification Principles

  • Combinational explosion in test vectors

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Test Vector, Test Benches and Harness

  • Test vectors are a set of patterns applied to inputs and a set of expected outputs. Both logic verification and manufacturing test require a good set of test vectors.
  • A verification test bench or harness is a piece of HDL code that is placed as a wrapper around a core piece of HDL to apply and check test vectors.
  • In the simplest test bench, input vectors are applied to the module under test and at each cycle, the outputs are examined to determine whether they comply with a predefined expected data set.

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Regression Testing ,Bug Tracking

  • High-level language scripts are frequently used when running large testbenches, especially for regression testing.
  • Regression testing involves performing a suite of simulations to automatically verify that no functionality has inadvertently changed in a module or set of modules.
  • Another important tool to use during verification (and in fact the whole design cycle) is a bug-tracking system. Bug-tracking systems such as the Unix/Linux based GNATS allow the management of a wide variety of bugs.
  • In these systems, each bug is entered and the location, nature, and severity of the bug noted. The bug discoverer is noted, along with the perceived person responsible for fixing the bug.

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Manufacturing Tests

  • Whereas verification or functionality tests seek to confirm the function of a chip as a whole, manufacturing tests are used to verify that every gate operates as expected.
  • The need to do this arises from a number of manufacturing defects that might occur either chip fabrication or accelerated life testing (where the chip is stressed by over-voltage and over-temperature operation).
  • Typical defects include the following:
  • Layer-to-layer shorts
  • Discontinuous wires
  • Missing or damaged vias Shorts through the thin gate oxide to the substrate or well.

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SEM images Manufacturing Defects

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Design for Testability (DFT)

  • Two key concepts
    1. Controllability
    2. Observability
  • These concepts ensure provision of means of setting and resetting key nodes and observing the response at key points
  • Failure during testing at chip level may be due to design defect or poorly controlled fabrication process
  • DUT (Device Under Test) are subjected to test pattern ( Test Vector)
  • Test patterns (Set of Binary Values) are generated by Automatic Test Pattern Generator (ATPG)
  • Response observed, faults detected

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Test Coverage

  • Detecting all the possible faults in DUT corresponds to 100% ‘Test coverage’
  • It is easy to detect first 80% of faults using classical test strategies
  • Generally it is not possible to anticipate 100% of all faults
  • Faults may be classified using different models
    • Mathematical model
    • Logical model (Stuck-at)
    • Physical model

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Nature of Failure

  • Failure may occur after cmos circuit fabricated & successfully passed test such failure due to
    • Poor design
    • Weakness induced during fabrication
    • Ageing or corrosion
  • Design faults are difficult to detect – make circuit open/short circuit other failures
    • Oxide Breakdown
    • Hot carrier injection

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Nature of Faults

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Testing Combinational Logic

  • Generate a set of test patterns which will detect all possible fault conditions
  • To test N input circuit, need to generate all possible 2N input signal combinations
  • N- bit counter (Controllability) and Observe output (Observability). It is exhaustive test & very effective only if N is small
  • N 2N 2N X 0.1µs =
  • 32 232 232 X 10-7 Sec =
  • 40 240 240 X 10-7 Sec =
  • 64 264 264 X 10-7 Sec =

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Sensitized Path-based Testing

  • Basic idea is to select a path from the site of possible fault, through a sequence of gates leading to an output of the logic circuit under test
  • Manifestation: Input at a site of assumed fault, say a ‘stuck at’ (SA) fault. Specified to generate the opposite value of assumed SA value (0 for SA1, 1 for SA0)
  • Propagation: Input of other gate are determined as to propagate the fault signal along the selected path to output of circuit. By setting And/Nand to 1, and Or/Nor to 0
  • Consistency (Justification): All primary input patterns are found by tracing backwards from input to primary input

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Testing Sequential Circuit

  • Complexity of testing sequential circuits are
    • Feedback loops
    • Placing a circuit in a known state
    • Timing problems

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Scan Design Techniques

  • Scan-path design is to reduce test generation complexity for circuit containing storage devices and feedback path with combinational logic

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  • The philosophy is to divide & conquer with the purpose to :

1. Set any internal state easily

2. Observe any state through a distinguishing sequence

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Scan Path

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SFF

SFF

SFF

Combinational

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logic

PI

PO

SCANOUT

SCANIN

TC or TCK

SFFs (scan Flip-flops)

Not shown: CK

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Level-sensitive Scan Design (LSSD)

  • Level sensitive means that state changes in FSM are independent of delays nor order of changes in input signals (if inputs are set to new values)
  • Scan is ability to shift into or out of any state
  • All internal storage is implemented using hazard free polarity-hold switches

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L1

L1

L2

C

D

A

B

SCAN-IN

L2

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Boundary Scan Test (BST)

  • BST consists of placing a scan path ( Shift Register) cell adjacent to each component pin and interconnect the cells so as to form a chain around the border of the circuit
  • Boundary scan path is provided with serial input and output pads which helps in,
    • Test the interconnections between various chips
    • Deliver data to chip for self testing
    • Test the chips themselves with internal self-test
  • the advantage of BST are,
    • No need for complex testers
    • Testing is simplified with respect to time and pattern generation

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Built-In-Self-Test (BIST)

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BIST controller

TP generation and application

Response capture / evaluation

Internal circuit under test

Access to BIST functions

Primary inputs

Primary outputs

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Built-In-Self-Test (BIST)

  • BIST Objectives are
    • To reduce test pattern generation cost
    • To reduce the volume of test data
    • To reduce the test time
  • BIST aims to integrate an automatic test system into the chip
    • Compact Test: Signature Analysis
    • Linear Feedback Shift Register (LFSR)
    • Built-in Logic Block Observer (BILBO)
    • Self-checking techniques

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Signature Analysis

  • For a large number of inputs, number of test vectors will be more. The time will also increase
  • Identification of some binary pattern
  • Identification is generated by applying set of test vectors and store the individual results and a number or encryption for the pattern
  • If any of the device is not functioning and result pattern will be different and does not match with the signature pattern. Can say that circuit is faulty
  • Advantage, result is in very compact form

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Linear Feedback Shift Register (LFSR)

  • Consists of long shift registers, with serial input generated by taking Exclusive OR of some of the intermediate value
  • Random Values

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Built-In Logic Block Observer (BILBO)

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  • Offers four separate functionalities

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BILBO ( B1 = B2 = 0)�Serial Scan Mode

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BILBO ( B1 = 0, B2 = 1)�Pattern Generator

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BILBO ( B1 = 1, B2 = 0)�Normal Mode

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BILBO ( B1 = B2 = 1)�Multiple Input Signature Register

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Self-Checking Techniques

  • Self-checking techniques consists of supplying coded input data to the logic block under test and comparing the output in a checker designed to detect any errors
  • The code used in data encoding depends on the type of errors
    • Simple error: One bit only affected at a time
    • Unidirectional error: Multiple bits at 1 instead of 0
    • Multiple error: Multiple bits affected in any order

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Text Books

  • 1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang & Yosuf Leblebici, Third Edition, Tata McGraw-Hill.
  • 2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste, and David Money Harris4th Edition, Pearson Education.

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  • Note : Images and figures have been taken from prescribed textbooks.

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Reference Books

  • 1. Adel Sedra and K. C. Smith, “Microelectronics Circuits Theory and Applications”, 6th or 7th Edition, Oxford University Press, International Version, 2009.
  • 2. Douglas A Pucknell & Kamran Eshragian, “Basic VLSI Design”, PHI 3rd Edition, (original Edition – 1994).
  • 3. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, TMH, 2007.

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