UHDM

Universal Hardware Data Model

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Interface in between parsers (Surelog…) and tools

For every SystemVerilog Object in the IEEE 1800-2017 Object Model, this tool automatically creates:

• a C++ class,
• corresponding VPI access (vpi_iterate, vpi_get, vpi_handle…)
• Serialization using Cap’n Proto mechanism
• An Elaborator/Uniquifier
• A Listener
• A Decompiler (Walker)

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How?

• The Object Model is captured in a YAML like form
• A script generates all the code automatically.
• In-memory data model is read/write even after deserialization

github.com/alainmarcel/UHDM

UHDM

module.yaml

….

gen_model.tcl

module.h

moduleFactory

vpi_user.cpp

vpi_iterate(vpiModule,NULL)

UHDM.capnp

CAPNP

UHDM serial.cpp

….

GCC

libuhdm.a

UHDM

Verible

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SystemVerilog Design

libuhdm.a

...

Surelog

On disk- �Serialized Design expressed with�the full SystemVerilog Object Model

Yosys

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...

libuhdm.a

- Simulation results

- Gate level netlist

...

Parsers

Tools

Verilator

First parser supporting UHDM database: Surelog

UHDM

SystemVerilog Parser + Preprocessor

github.com/alainmarcel/Surelog

Written in C++

ANTLR with multithreaded + incremental

Semantic checks, Datatype binding, Design & UVM Elaboration, Python API, UHDM on-disk compiled output

Future?

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U

H

D

M

Verible

SystemVerilog Design

Surelog

Yosys

Parsers

Frontend

“Language Support”

Backend

Synthesizable

VHDL

Chisel

Backend

Simulatable

Verilator

Icarus

Synthesizable

Bridge

New distributed

Simulator 1

UVM

Feature

Extraction

Common Functionality

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Counters / Muxes / etc

New distributed

Simulator 2

New distributed

Simulator 3